THS1031IPW Datasheet, PDF (17/41 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
PRINCIPLES OF OPERATION
full external reference mode (mode = AGND) (continued)
+FS
AVDD
2 _–FS
AVDD
AIN REFSENSE
REFTS
_
REFT = ^AVDD
2
+ [(FS+) – (FS–)] × ^GAIN
2
+
_
REFB = ^AVDD
2
– [(FS+) – (FS–)] × ^GAIN
2
+
REFBS
REFTF
0.1 µF
10 µF
0.1 µF
0.1 µF
REFBF
MODE
Figure 14. Full External Reference With Kelvin Connections
differential mode (mode = AV_DD/2)
AVDD + VREF
REFTF =
2
AIN–
AIN+
REFTS
REFBS
1
Sample
–1/2 and
–1/2 ^Hold
PGA
ADC
Core
VREF
AGND
Internal
Reference
Buffer
AVDD – VREF
REFBF =
2
Figure 15. ADC Reference Generation, MODE = AV_DD/2
When MODE = AV_DD/2, the internal reference buffer is enabled, its outputs internally switched to REFTF and
REFBF and inputs internally switched to VREF and AGND as shown in Figure 15. The REFTF and REFBF
voltages are centered on AV_DD/2 by the internal reference buffer and the voltage difference between REFTF
and REFBF equals the voltage at VREF. The internal REFTS to REFBS and REFTF to REFBF switches are
open in this mode, allowing REFTS and REFBS to form the AIN– to the sample and hold.
Depending on the connection of the REFSENSE pin, the voltage on VREF may be externally driven, or set to
an internally generated voltage of 1 V, 2 V, or an intermediate voltage (see the onboard reference generator
configuration).
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