THS1031IPW Datasheet, PDF (19/41 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
PRINCIPLES OF OPERATION
top/bottom mode (MODE = AV_DD)
REFTF = AVDD + (REFTS – REFBS)
2
AIN+
REFTS
REFBS
1
Sample
–1/2 and
–1/2 ^Hold
PGA
ADC
Core
Internal
Reference
Buffer
REFBF = AVDD – (REFTS – REFBS)
2
Figure 18. ADC Reference Generation Mode = AV_DD
Connecting MODE to AV_DD enables the internal reference buffer. Its inputs are internally switched to the REFTS
and REFBS pins and its outputs internally switched to pins REFTF and REFBF. The internal connections
(REFTS to REFTF) and (REFBS to REFBF) are broken.
To match the signal span to the full ADC input span, the voltage difference between REFTS and REFBS should
be REFTS – REFBS = [(FS+) – (FS–)] × Gain, with the average of the REFTS and REFBS voltages being the
AIN midscale voltage, VM.
Typically, REFSENSE is tied to AV_DD to disable the ORG output to VREF (as in Figure 19), but the user can
choose to use the ORG output to VREF as either REFTS or REFBS.
AVDD
+FS
–FS
DC SOURCE = VM + [(FS+) – (FS–)] × ^GAIN
2
GAIN
DC SOURCE =VM – [(FS+) – (FS–)] ×
2
AIN
MODE
REFTS REFSENSE
REFBS
0.1 µF
REFTF
0.1 µF
10 µF 0.1 µF
REFBF
Figure 19. ADC Reference Generation Mode = AV_DD
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