DM3730_10 Datasheet, PDF (32/268 Pages) Texas Instruments – Applications Processor

DM3730, DM3725
SPRS685 – AUGUST 2010
www.ti.com
BALL
BOTTOM
[1]
N28
M27
N27
N26
N25
P28
P27
P26
R27
R25
AE2
AG5
AH5
AH4
AG4
AF4
AE4
Table 2-1. Ball Characteristics (CBP Pkg.)⁽³⁾ (continued)
BALL TOP
[2]
PIN NAME [3]
NA
mmc1_clk
gpio_120 ⁽¹⁾
safe_mode
NA
mmc1_cmd
gpio_121 ⁽¹⁾
safe_mode
NA
mmc1_dat0
gpio_122 ⁽¹⁾
safe_mode
NA
mmc1_dat1
gpio_123⁽¹⁾
safe_mode
NA
mmc1_dat2
gpio_124⁽¹⁾
safe_mode
NA
mmc1_dat3
gpio_125⁽¹⁾
safe_mode
NA
gpio_126⁽¹⁾
safe_mode
NA
gpio_127⁽¹⁾
safe_mode
NA
gpio_128⁽¹⁾
safe_mode
NA
gpio_129⁽¹⁾
safe_mode
NA
mmc2_clk
mcspi3_clk
gpio_130
safe_mode
NA
mmc2_cmd
mcspi3_simo
gpio_131
safe_mode
NA
mmc2_dat0
mcspi3_somi
gpio_132
safe_mode
NA
mmc2_dat1
gpio_133
safe_mode
NA
mmc2_dat2
mcspi3_cs1
gpio_134
safe_mode
NA
mmc2_dat3
mcspi3_cs0
gpio_135
safe_mode
NA
mmc2_dat4
mmc2_dir_dat0
mmc3_dat0
gpio_136
safe_mode
MODE [4] TYPE [5]
0
IO
4
IO
7
0
O
4
IO
7
0
IO
4
IO
7
0
IO
4
IO
7
0
IO
4
IO
7
0
IO
4
IO
7
4
IO
7
4
IO
7
4
IO
7
4
IO
7
0
IO
1
IO
4
IO
7
0
O
1
IO
4
IO
7
0
IO
1
IO
4
IO
7
0
IO
4
IO
7
0
IO
1
O
4
IO
7
0
IO
1
IO
4
IO
7
0
IO
1
O
3
IO
4
IO
7
BALL
RESET
STATE [6]
L
BALL
RESET
REL.
STATE [7]
L
RESET
REL. MODE POWER [9] HYS [10]
[8]
7
vdds_mmc1 Yes
L
L
7
vdds_mmc1 Yes
L
L
7
vdds_mmc1 Yes
L
L
7
vdds_mmc1 Yes
L
L
7
vdds_mmc1 Yes
L
L
7
vdds_mmc1 Yes
L
L
7
vdds_x
Yes
L
L
7
vdds_x
Yes
L
L
7
vdds
Yes
L
L
7
vdds_x
Yes
L
L
7
vdds
Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
L
L
7
vdds
Yes
BUFFER
STRENG
TH (mA)
[11]
1
1
1
1
1
1
1
1
4
1
4
4
4
4
4
4
4
PULLUP
/DOWN
TYPE [12]
IO CELL
[13]
PU/ PD⁽⁵⁾ LVCMOS
PU/ PD⁽⁵⁾ LVCMOS
PU/ PD ⁽⁵⁾ LVCMOS
PU/ PD⁽⁵⁾ LVCMOS
PU/ PD ⁽⁵⁾ LVCMOS
PU/ PD ⁽⁵⁾ LVCMOS
PU/ PD ⁽⁵⁾ LVCMOS
PU/ PD⁽⁵⁾ LVCMOS
PU/ PD
LVCMOS
PU/ PD⁽⁵⁾ LVCMOS
PU/ PD
LVCMOS
PU/ PD
LVCMOS
PU/ PD
LVCMOS
PU/ PD
LVCMOS
PU/ PD
LVCMOS
PU/ PD
LVCMOS
PU/ PD
LVCMOS
32
TERMINAL DESCRIPTION
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