DM3730_10 Datasheet, PDF (245/268 Pages) Texas Instruments – Applications Processor

DM3730, DM3725
www.ti.com
SPRS685 – AUGUST 2010
MMC1
MMC2
sdmmc1_clk
MMC5
MMC5
sdmmc1_cmd
MMC6
MMC6
sdmmc1_dat[3:0]
SWPS038-103
Figure 6-66. MMC1 Interface—Standard MMC and MMC Identification Modes—Data/Command Transmit
6.6.8.1.5 MMC1 Interface—High-Speed MMC Mode
Table 6-115 and Table 6-116 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 6-67 and Figure 6-68).
Table 6-114. MMC1 Interface Timing Conditions—High-Speed MMC Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
Output Conditions
C_LOAD
Output load capacitance⁽¹⁾
(1) The load setting of the IO buffer: SPEEDCTRL = 1.
VALUE
3
3
30
UNIT
ns
ns
pF
Table 6-115. MMC1 Interface Timing Requirements—High-Speed MMC Mode^{(2) (3) (4) (5)}
NO.
PARAMETER
OPP100
OPP50
MIN
MAX
MIN
MAX
MMC1 Interface (1.8-V IO)
MMC3 t_{su(CMDV-CLKIH)} Setup time, mmc1_cmd valid before mmc1_clk rising
5.6
clock edge
26.0
MMC4 t_{h(CLKIH-CMDIV)} Hold time, mmc1_cmd valid after mmc1_clk rising
2.3
clock edge
MMC7 t_{su(DATxV-CLKIH)} Setup time, mmc1_dat[n:0]⁽¹⁾ valid before mmc1_clk
5.6
rising clock edge
MMC8 t_{h(CLKIH-DATxIV)} Hold time, mmc1_dat[n:0]⁽¹⁾ valid after mmc1_clk
2.3
rising clock edge
1.9
26.0
1.9
MMC1 Interface (3.0-V IO)
MMC3 t_{su(CMDV-CLKIH)} Setup time, mmc1_cmd valid before mmc1_clk rising
5.6
clock edge
26.0
MMC4 t_{h(CLKIH-CMDIV)} Hold time, mmc1_cmd valid after mmc1_clk rising
2.3
clock edge
MMC7 t_{su(DATxV-CLKIH)} Setup time, mmc1_dat[n:0]⁽¹⁾ valid before mmc1_clk
5.6
rising clock edge
MMC8 t_{h(CLKIH-DATxIV)} Hold time, mmc1_dat[n:0]⁽¹⁾ valid after mmc1_clk
2.3
rising clock edge
1.9
26.0
1.9
(1) In mmc1_dat[n:0], n is equal to 3.
(2) Timing parameters are referred to output clock specified in Table 6-116.
(3) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-116.
(4) Corresponding figures showing timing parameters are common with the Standard MMC mode figures.
(5) See Section 4.3.4, Processor Clocks.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Copyright © 2010, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 245
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