DM3730_10 Datasheet, PDF (166/268 Pages) Texas Instruments – Applications Processor

DM3730, DM3725
SPRS685 – AUGUST 2010
www.ti.com
Table 6-7. GPMC/NOR Flash Timing Requirements—Asynchronous Mode⁽⁷⁾
NO.
PARAMETER
OPP100
OPP50
UNIT
FA5⁽¹⁾
FA20⁽³⁾
FA21⁽²⁾
t_acc(d)
t_{acc1-pgmode(d)}
t_{acc2-pgmode(d)}
Data access time
Page mode successive data access time
Page mode first data access time
MIN
MAX
MIN
MAX
H⁽⁵⁾
H⁽⁵⁾
ns
P⁽⁴⁾
P⁽⁴⁾
ns
H⁽⁵⁾
H⁽⁵⁾
ns
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(3) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock
edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(4) P = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK⁽⁶⁾
(5) H = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK⁽⁶⁾
(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(7) See Section 4.3.4, Processor Clocks.
Table 6-8. GPMC/NOR Flash Switching Characteristics—Asynchronous Mode⁽¹⁶⁾
NO.
FA0
t_R(d)
t_F(d)
t_w(nbeV)
FA1
t_w(ncsV)
FA3
t_{d(ncsV-nadvIV)}
FA4
t_{d(ncsV-noeIV)}
FA9
t_d(aV-ncsV)
FA10 t_d(nbeV-ncsV)
FA12 t_{d(ncsV-nadvV)}
FA13 t_d(ncsV-noeV)
FA14 t_{d(ncsV-iodir)}
FA15 t_{d(ncsV-iodir)}
PARAMETER
OPP100
OPP50
MIN
MAX
MIN
MAX
Rise time, output data gpmc_d[15:0]
2
2
Fall time, output data gpmc_d[15:0]
Pulse duration, output lower-byte
enable/command latch enable
gpmc_nbe0_cle, output
upper-byte enable gpmc_nbe1
valid time
Read
Write
Pulse duration, output chip select Read
gpmc_ncsx⁽¹³⁾ low
Write
Delay time, output chip select
gpmc_ncsx⁽¹³⁾ valid to output
address valid/address latch
enable gpmc_nadv_ale invalid
Read
Write
Delay time, output chip select gpmc_ncsx⁽¹³⁾
valid to output enable gpmc_noe invalid
(Single read)
Delay time, output address gpmc_a[27:1] valid
to output chip select gpmc_ncsx⁽¹³⁾ valid
Delay time, output lower-byte
enable/command latch enable
gpmc_nbe0_cle, output upper-byte enable
gpmc_nbe1 valid to output chip select
gpmc_ncsx⁽¹³⁾ valid
Delay time, output chip select gpmc_ncsx⁽¹³⁾
valid to output address valid/address latch
enable gpmc_nadv_ale valid
Delay time, output chip select gpmc_ncsx⁽¹³⁾
valid to output enable gpmc_noe valid
Delay time, output chip select gpmc_ncsx⁽¹³⁾
valid to output IO direction control gpmc_io_dir
high
Delay time, output chip select gpmc_ncsx⁽¹³⁾
valid to output IO direction control gpmc_io_dir
low
2
N⁽¹²⁾
N⁽¹²⁾
A⁽¹⁾
A⁽¹⁾
B⁽²⁾ – 0.2 B⁽²⁾ + 2.0
B⁽²⁾ – 0.2 B⁽²⁾ + 2.0
C⁽³⁾ – 0.2 C⁽³⁾ + 2.0
J⁽⁹⁾ – 0.2 J⁽⁹⁾ + 2.0
J⁽⁹⁾ – 0.2 J⁽⁹⁾ + 2.0
K⁽¹⁰⁾ – 0.2 K⁽¹⁰⁾ + 2.0
L⁽¹¹⁾ – 0.2 L⁽¹¹⁾ + 2.0
L⁽¹¹⁾ – 0.2 L⁽¹¹⁾ + 2.0
M⁽¹⁴⁾ – 0.2 M⁽¹⁴⁾ + 2.0
2
N⁽¹²⁾
N⁽¹²⁾
A⁽¹⁾
A⁽¹⁾
B⁽²⁾ – 0.2 B⁽²⁾ + 2.6
B⁽²⁾ – 0.2 B⁽²⁾ + 2.6
C⁽³⁾ – 0.2 C⁽³⁾ + 2.6
J⁽⁹⁾ – 0.2 J⁽⁹⁾ + 2.6
J⁽⁹⁾ – 0.2 J⁽⁹⁾ + 2.6
K⁽¹⁰⁾ – 0.2 K⁽¹⁰⁾ + 2.6
L ⁽¹¹⁾ – 0.2 L⁽¹¹⁾ + 2.6
L⁽¹¹⁾ – 0.2 L⁽¹¹⁾ + 2.6
M⁽¹⁴⁾ – 0.2 M⁽¹⁴⁾ + 2.6
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
166 Timing Requirements and Switching Characteristics
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