DM3730_10 Datasheet, PDF (175/268 Pages) Texas Instruments – Applications Processor

DM3730, DM3725
www.ti.com
SPRS685 – AUGUST 2010
Table 6-12. GPMC/NAND Flash Switching Characteristics—Asynchronous Mode⁽¹⁵⁾
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
t_R(d)
Rise time, output data gpmc_d[15:0]
2
2
ns
GNF0
t_F(d)
t_w(nweV)
Fall time, output data gpmc_d[15:0]
Pulse duration, output write enable gpmc_nwe
valid
2
A⁽¹⁾
2
ns
A⁽¹⁾
ns
GNF1 t_d(ncsV-nweV)
Delay time, output chip select gpmc_ncsx⁽¹³⁾ B⁽²⁾ – 0.2 B⁽²⁾ + 2.0 B⁽²⁾ – 0.2 B⁽²⁾ + 2.6
ns
valid to output write enable gpmc_nwe valid
GNF2 t_w(cleH-nweV)
Delay time, output lower-byte
C⁽³⁾ – 0.2 C⁽³⁾ + 2.0 C⁽³⁾ – 0.2 C⁽³⁾ + 2.6
ns
enable/command latch enable gpmc_nbe0_cle
high to output write enable gpmc_nwe valid
GNF3 t_w(nweV-dV)
Delay time, output data gpmc_d[15:0] valid to D⁽⁴⁾ – 0.2 D⁽⁴⁾ + 2.0 D⁽⁴⁾ – 0.2 D⁽⁴⁾ + 2.6
ns
output write enable gpmc_nwe valid
GNF4 t_w(nweIV-dIV)
Delay time, output write enable gpmc_nwe
E⁽⁵⁾ – 0.2 E⁽⁵⁾ + 2.0 E⁽⁵⁾ – 0.2 E⁽⁵⁾ + 2.6
ns
invalid to output data gpmc_d[15:0] invalid
GNF5 t_{w(nweIV-cleIV)}
Delay time, output write enable gpmc_nwe
F⁽⁶⁾ – 0.2 F⁽⁶⁾ + 2.0 F⁽⁶⁾ – 0.2 F⁽⁶⁾ + 2.6
ns
invalid to output lower-byte enable/command
latch enable gpmc_nbe0_cle invalid
GNF6 t_{w(nweIV-ncsIV)}
Delay time, output write enable gpmc_nwe
G⁽⁷⁾ – 0.2 G⁽⁷⁾ + 2.0 G⁽⁷⁾ – 0.2 G⁽⁷⁾ + 2.6
ns
invalid to output chip select gpmc_ncsx⁽¹³⁾
invalid
GNF7 t_w(aleH-nweV)
Delay time, output address valid/address latch C⁽³⁾ – 0.2 C⁽³⁾ + 2.0 C⁽³⁾ – 0.2 C⁽³⁾ + 2.6
ns
enable gpmc_nadv_ale high to output write
enable gpmc_nwe valid
GNF8 t_{w(nweIV-aleIV)}
Delay time, output write enable gpmc_nwe
F⁽⁶⁾ – 0.2 F⁽⁶⁾ + 2.0 F⁽⁶⁾ – 0.2 F⁽⁶⁾ + 2.6
ns
invalid to output address valid/address latch
enable gpmc_nadv_ale invalid
GNF9 t_c(nwe)
Cycle time, write
H⁽⁸⁾
H⁽⁸⁾
ns
GNF10 t_d(ncsV-noeV)
Delay time, output chip select gpmc_ncsx⁽¹³⁾ I⁽⁹⁾ – 0.2 I⁽⁹⁾ + 2.0 I⁽⁹⁾ – 0.2 I⁽⁹⁾ + 2.6
ns
valid to output enable gpmc_noe valid
GNF13 t_w(noeV)
Pulse duration, output enable gpmc_noe valid
K⁽¹⁰⁾
K⁽¹⁰⁾
ns
GNF14 t_c(noe)
Cycle time, read
L⁽¹¹⁾
L⁽¹¹⁾
ns
GNF15 t_{w(noeIV-ncsIV)}
Delay time, output enable gpmc_noe invalid to M⁽¹²⁾ – 0.2 M⁽¹²⁾ + 2.0 M⁽¹²⁾ – 0.2 M⁽¹²⁾ + 2.6
ns
output chip select gpmc_ncsx⁽¹³⁾ invalid
(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK⁽¹⁴⁾
(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK⁽¹⁴⁾
(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK⁽¹⁴⁾
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay) * GPMC_FCLK⁽¹⁴⁾
(5) E = ((WrCycleTime – WEOffTime) * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay) * GPMC_FCLK⁽¹⁴⁾
(6) F = ((ADVWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay)) * GPMC_FCLK⁽¹⁴⁾
(7) G = ((CSWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay)) * GPMC_FCLK⁽¹⁴⁾
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK⁽¹⁴⁾
(9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK⁽¹⁴⁾
(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK⁽¹⁴⁾
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK⁽¹⁴⁾
(12) M = ((CSRdOffTime – OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay)) * GPMC_FCLK⁽¹⁴⁾
(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) See Section 4.3.4, Processor Clocks.
Copyright © 2010, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 175
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