CC2550 Datasheet, PDF (32/50 Pages) Texas Instruments – Single Chip Low Cost Low Power RF-Transmitter

CC2550
32 Asynchronous and Synchronous Serial Operation
Several features and modes of operation have
been included in the CC2550 to provide
backward compatibility with previous Chipcon
products and other existing RF communication
systems. For new systems, it is recommended
to use the built-in packet handling features, as
they can give more robust communication,
significantly offload the microcontroller and
simplify software development.
The MCU must control start and stop of
transmit with the STX and SIDLE strobes.
The CC2550 modulator samples the level of the
asynchronous input 8 times faster than the
programmed data rate. The timing requirement
for the asynchronous stream is that the error in
the bit period must be less than one eighth of
the programmed data rate.
32.1 Asynchronous operation
For backward compatibility with systems
already using the asynchronous data transfer
from other Chipcon products, asynchronous
transfer is also included in CC2550. When
asynchronous transfer is enabled, several of
the support mechanisms for the MCU that are
included in CC2550 will be disabled, such as
packet handling hardware, buffering in the
FIFO and so on. The asynchronous transfer
mode does not allow the use of the data
whitener, interleaver and FEC.
Only 2-FSK, GFSK and OOK are supported for
asynchronous transfer.
Setting PKTCTRL0.PKT_FORMAT to 3
enables asynchronous transparent (serial)
mode.
In TX, the GDO0 pin is used for data input (TX
data).
32.2 Synchronous serial operation
In the Synchronous serial operation mode,
data is transferred on a two wire serial
interface. The CC2550 provides a clock that is
used to set up new data on the data input line.
Data input (TX data) is the GDO0 pin. This pin
will automatically be configured as an input
when TX is active.
Preamble and sync word insertion may or may
not be active, dependent on the sync mode set
by the MDMCFG2.SYNC_MODE . If preamble
and sync word is disabled, all other packet
handler features and FEC should also be
disabled. The MCU must then handle
preamble and sync word insertion in software.
If preamble and sync word insertion is left on,
all packet handling features and FEC can be
used. The CC2550 will insert the preamble and
sync word and the MCU will only provide the
data payload. This is equivalent to the
recommended FIFO operation mode.
33 Configuration Registers
The configuration of CC2550 is done by
programming 8-bit registers. The configuration
data based on selected system parameters
are most easily found by using the SmartRF^®
Studio software. Complete descriptions of the
registers are given in the following tables. After
chip reset, all the registers have default values
as shown in the tables.
There are nine Command Strobe Registers,
listed in Table 24. Accessing these registers
will initiate the change of an internal state or
mode. There are 30 normal 8-bit Configuration
Registers, listed in Table 25. Many of these
registers are for test purposes only, and need
not be written for normal operation of CC2550.
There are also six Status registers, which are
listed in Table 26. These registers, which are
read-only, contain information about the status
of CC2550.
The TX FIFO is accessed through one 8-bit
register. Only write operations are allowed to
the TX FIFO.
During the address transfer and while writing
to a register or the TX FIFO, a status byte is
returned. This status byte is described in Table
15 on page 17.
Table 27 summarizes the SPI address space.
Registers that are only defined on the CC2500
transceiver are also listed. CC2500 and CC2550
are register compatible, but registers and fields
only implemented in the transceiver always
contain zero on CC2550.
The address to use is given by adding the
base address to the left and the burst and
Preliminary Data Sheet (rev. 1.1) SWRS039
Page 32 of 51