CC2550 Datasheet, PDF (16/50 Pages) Texas Instruments – Single Chip Low Cost Low Power RF-Transmitter

CC2550
counter is used to control the access to the
table. This counter is incremented each time a
byte is read or written to the table, and set to
the lowest index when CSn is high. When the
highest value is reached the counter restarts at
zero.
The access to the PATABLE is either single
byte or burst access depending on the burst
bit. When using burst access the index counter
will count up; when reaching 7 the counter will
restart at 0. The read/write bit controls whether
the access is a write access (R/W=0) or a read
access (R/W=1).
If one byte is written to the PATABLE and this
value is to be read out then CSn must be set
high before the read access in order to set the
index counter back to zero.
Note that the content of the PATABLE is lost
when entering the SLEEP state.
t _sp
t _ch
t _cl
t_sd
t_hd
t _ns
SCLK:
CSn:
Write to register:
SI ^X
0
A6
A5
A4
A3
A2
A1
A0 X D_W7 D_W6 D_W5 D_W4 D _W3 D_W2 D_W1 D _W0
X
SO ^{Hi-Z S7}
S6
S5
S4
S3
S2
S1
S0
S7
S6 S5 S4 S3 S2 S1 S0 S7 Hi-Z
Read from register:
SI ^X
1
A6 A5
A4 A3 A2 A1 A0
X
SO ^{Hi-Z S7}
S6
S5
S4
S3
S2
S1
S0
D _R7
D_R6 D_R5 D_R4 D_R3 D _R2 D_R1
D _R0
Hi-Z
Figure 6: Configuration registers write and read operations
Parameter
F_SCLK
t_sp,pd
t_sp
t_ch
t_cl
t_rise
t_fall
t_sd
t_hd
t_ns
Description
SCLK frequency
CSn low to positive edge on SCLK, in power-down mode
CSn low to positive edge on SCLK, in active mode
Clock high
Clock low
Clock rise time
Clock rise time
Setup data to positive edge on SCLK
Hold data after positive edge on SCLK
Negative edge on SCLK to CSn high.
Min
0
TBDµs
TBDns
50ns
50ns
-
-
TBDns
TBDns
TBDns
Table 14: SPI interface timing requirements
Max
10MHz
-
-
-
-
TBDns
TBDns
-
-
-
Preliminary Data Sheet (rev. 1.1) SWRS039
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