DRV8711 Datasheet, PDF (3/34 Pages) Texas Instruments – STEPPER MOTOR CONTROLLER IC

DRV8711
www.ti.com
NAME
GND
VM
VINT
V5
CP1
CP2
VCP
SLEEPn
STEP/AIN1
DIR/AIN2
BIN1
BIN2
RESET
SCS
SCLK
SDATI
SDATO
STALLn/
BEMFVn
FAULTn
BEMF
A1HS
AOUT1
A1LS
A2HS
AOUT2
A2LS
AISENP
AISENN
B1HS
SLVSC40 – JUNE 2013
NO.
5, 29,
38,
PPAD
4
7
6
1
2
3
8
10
11
12
13
9
16
14
15
17
19
18
20
36
37
35
31
30
32
34
33
27
I/O ⁽¹⁾
-
TERMINAL FUNCTIONS
DESCRIPTION
EXTERNAL COMPONENTS OR CONNECTIONS
POWER AND GROUND
Device ground
All pins must be connected to ground
- Bridge A power supply
Connect to motor supply voltage. Bypass to GND with a 0.01-μF
ceramic capacitor plus a 100-μF electrolytic capacitor.
- Internal logic supply voltage
Logic supply voltage. Bypass to GND with a 1-μF 6.3-V X7R ceramic
capacitor.
O 5-V regulator output
5-V linear regulator output. Bypass to GND with a 0.1-μF 10-V X7R
ceramic capacitor.
IO Charge pump flying capacitor
IO Charge pump flying capacitor
Connect a 0.1-μF X7R capacitor between CP1 and CP2. Voltage
rating must be greater than applied VM voltage.
IO High-side gate drive voltage
Connect a 1-μF 16-V X7R ceramic capacitor to VM
CONTROL
I Sleep mode input
Logic high to enable device, logic low to enter low-power sleep mode
I Step input/Bridge A IN1
Indexer mode: Rising edge causes the indexer to move one step.
External PWM mode: controls bridge A OUT1 Internal pulldown.
I Direction input/Bridge A IN2
Indexer mode: Level sets the direction of stepping.
External PWM mode: controls bridge A OUT2 Internal pulldown.
I Bridge B IN1
Indexer mode: No function
External PWM mode: controls bridge B OUT1 Internal pulldown.
I Bridge B IN2
Indexer mode: No function
External PWM mode: controls bridge B OUT2 Internal pulldown.
I Reset input
Active-high reset input initializes all internal logic and disables the H-
bridge outputs. Internal pulldown.
SERIAL INTERFACE
I Serial chip select input
Active high to enable serial data transfer. Internal pulldown.
I Serial clock input
Rising edge clocks data into part for write operations. Falling edge
clocks data out of part for read operations. Internal pulldown.
I Serial data input
Serial data input from controller. Internal pulldown.
O Serial data output
Serial data output to controller. Open-drain output requires external
pull-up.
STATUS
OD Stall/Back EMF valid
Internal stall detect mode: logic low when motor stall detected.
External stall detect mode: Active low when valid back EMF
measurement is ready.
Open-drain output requires external pullup.
OD Fault
Logic low when in fault condition. Open-drain output requires external
pullup.
Faults: OCP, PDF, OTS, UVLO
O Back EMF
Analog output voltage represents motor back EMF. Place a 1-nF low-
leakage capacitor to ground on this pin.
OUTPUTS
O Bridge A out 1 HS gate
Connect to gate of HS FET for bridge A out 1
I Bridge A output 1
Connect to output node of external FETs of bridge A out 1
O Bridge A out 1 LS gate
Connect to gate of LS FET for bridge A out 1
O Bridge A out 2 HS gate
Connect to gate of HS FET for bridge A out 2
I Bridge A output 2
Connect to output node of external FETs of bridge A out 2
O Bridge A out 2 LS gate
Connect to gate of LS FET for bridge A out 2
I Bridge A Isense + in
Connect to current sense resistor for bridge A
I Bridge A Isense - in
Connect to ground at current sense resistor for bridge A
O Bridge B out 1 HS gate
Connect to gate of HS FET for bridge B out 1
(1) Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input/output
Copyright © 2013, Texas Instruments Incorporated
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