DRV8711 Datasheet, PDF (16/34 Pages) Texas Instruments – STEPPER MOTOR CONTROLLER IC

DRV8711
SLVSC40 – JUNE 2013
www.ti.com
Blanking Time
After the current is enabled in an H-bridge, the voltage on the ISEN pin is ignored for a period of time before
enabling the current sense circuitry. This blanking time is adjustable from 1 µS to 5.12 µs, in 20 ns increments,
by setting the TBLANK bits in the BLANK register. Note that the blanking time also sets the minimum on time of
the PWM.
The same blanking time is applied to the fast decay period in auto decay mode. The PWM will ignore any
transitions on Itrip after entering fast decay mode, until the blanking time has expired.
To provide better current control at very low current steps, an adaptive blanking time mode can be enabled by
setting the ABT bit in the BLANK register. If ABT is set, at current levels below 30% of full scale current (as
determined by the step table), the blanking time (so also the minimum on time) is cut in half, to 50% of the value
programmed by the TBLANK bits.
For higher degrees of micro-stepping it is recommended to enable ABT bit for better current regulation.
Pre-Drivers
An internal charge pump circuit and pre-drivers inside the DRV8711 directly drive N-channel MOSFETs, which
drive the motor current.
The peak drive current of the pre-drivers is adjustable by setting the bits in the DRIVE register. Peak source
currents may be set to 50 mA, 100 mA, 150 mA, or 200 mA. The peak sink current is approximately 2x the peak
source current. Adjusting the peak current will change the output slew rate, which also depends on the FET input
capacitance and gate charge.
When changing the state of the output, the peak current is applied for a short period of time (tDRIVE), to charge
the gate capacitance. After this time, a weak current source is used to keep the gate at the desired state. When
selecting the gate drive strength for a given external FET, the selected current must be high enough to fully
charge and discharge the gate during the time when driven at full current, or excessive power will be dissipated
in the FET.
During high-side turn-on, the low-side gate is pulled low. This prevents the gate-source capacitance of the low-
side FET from inducing turn-on.
The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. Additional dead time is added with digital delays. This delay
can be selected by setting the DTIME bits in the CTRL register.
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