DRV8711 Datasheet, PDF (23/34 Pages) Texas Instruments – STEPPER MOTOR CONTROLLER IC

DRV8711
www.ti.com
SLVSC40 – JUNE 2013
Protection Circuits
The DRV8711 is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
Overcurrent is sensed by monitoring the voltage drop across the external FETs. If the voltage across a driven
FET exceeds the value programmed by the OCPTH bits in the DRIVE register for more than the time period
specified by the OCPDEG bits in the DRIVE register, an OCP event is recognized. When operating in direct
PWM mode, during an OCP event, the H-bridge experiencing the OCP event is disabled; if operating in indexer
mode, both H-bridges will be disabled. In addition, the corresponding xOCP bit in the STATUS register is set,
and the FAULTn pin is driven low. The H-bridge(s) will remain off, and the xOCP bit will remain set, until it is
written to 0, or the device is reset.
Pre-Driver Fault
If excessive current is detected on the gate drive outputs (which would be indicative of a failed/shorted output
FET or PCB fault), the H-bridge experiencing the fault is disabled, the xPDF bit in the STATUS register is set,
and the FAULTn pin is driven low. The H-bridge will remain off, and the xPDF bit will remain set until it is written
to 0, or the device is reset.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled, the OTS bit in the STATUS
register will be set, and the FAULTn pin will be driven low. Once the die temperature has fallen to a safe level
operation will automatically resume and the OTS bit will reset. The FAULTn pin will be released after operation
has resumed.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all FETs in the H-
bridge will be disabled, the UVLO bit in the STATUS register will be set, and the FAULTn pin will be driven low.
Operation will resume and the UVLO bit will reset when VM rises above the UVLO threshold. The FAULTn pin
will be released after operat ion has resumed.
During any of these fault conditions, the STEP input pin will be ignored.
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