DRV8711 Datasheet, PDF (21/34 Pages) Texas Instruments – STEPPER MOTOR CONTROLLER IC

DRV8711
www.ti.com
SLVSC40 – JUNE 2013
External Stall Detection
To use an external microcontroller to manage stall detection, the EXSTALL bit in the CTRL register is set to ‘1’.
In this mode, the STALLn / BEMFVn output pin is used to signal a valid back EMF measurement is ready. In
addition, the SDT and SDTLAT bits are also set at this time.
BEMFVn and BEMF are still valid outputs in this mode even if the step time is smaller than SMPLTH time.
When the BEMFVn pin goes active low, it is an indication that a valid back EMF voltage measurement is
available. This signal could be used, for example, to trigger an interrupt on a microcontroller. The microcontroller
can then sample the voltage present (using an A/D converter) on the BEMF pin.
After sampling the back EMF voltage, the microcontroller writes a ‘0’ to the SDTLAT bit to clear the SDT bit and
BEMFVn pin, in preparation for the next back EMF sample. If the SDTLAT bit is not cleared by the
microcontroller, it will automatically be cleared in the next zero-current step.
For either internal or external stall detection, at very high motor speeds when the PWM duty cycle approaches
100%, the inductance of the motor and the short duration of each step may cause the time required for current
recirculation to exceed the step time. In this case, back EMF will not be correctly sampled, and stall detection
cannot function. This condition occurs most at high degrees of micro-stepping, since the zero current step lasts
for a shorter duration. It is advisable to run the motor at lower degrees of micro-stepping at higher speeds to
allow time for current recirculation if stall detection is needed in this condition.
RESET and SLEEPn Operation
An internal power-up reset circuit monitors the voltage applied to the VM pin. If VM falls below the VM
undervoltage lockout voltage, the part is reset, as described below for the case of asserting the RESET pin.
If the RESET pin is asserted, all internal logic including the indexer is reset. All registers are returned to their
initial default conditions. The power stage will be disabled, and all inputs, including STEP and the serial interface,
are ignored when RESET is active.
On exiting reset state, some time (approximately 1 mS) needs to pass before the part is fully functional.
Applying an active low input to the SLEEPn input pin will place the device into a low power state. In sleep mode,
the motor driver circuitry is disabled, the gate drive regulator and charge pump are disabled, and all analog
circuitry is placed into a low power state. The digital circuitry in the device still operates, so the device registers
can still be accessed via the serial interface.
When SLEEPn is active, the RESET pin does not function. SLEEPn must be exited before RESET will take
effect.
When exiting from sleep mode, some time (approximately 1 mS) needs to pass before applying a STEP input, to
allow the internal circuitry to stabilize.
Copyright © 2013, Texas Instruments Incorporated
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