DRV8711 Datasheet, PDF (20/34 Pages) Texas Instruments – STEPPER MOTOR CONTROLLER IC

DRV8711
SLVSC40 – JUNE 2013
BEMF
buffer
STALLn/
BEMFVn
To
STATUS
register
SDCNT
2
counter
comp
reference
1.80 V
SDTHR
8
DAC
SDTHR
DAC
control
logic
2
VDIV
2
VDIV
2
VDIV
2
VDIV
VM
AOUT1
VM
AOUT2
VM
BOUT1
VM
BOUT2
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Step
Motor
Figure 8. Stall Detection
Internal Stall Detection
To use internal stall detection, the EXSTALL bit in the CTRL register is set to ‘0’. In this mode, the
STALLn/BEMFVn output pin is used to signal a valid stall condition.
Step time, or rate at which step input is applied to DRV8711, has to be greater than SMPLTH time for back EMF
sampling.
Using internal stall detection, a stall is detected when the sampled back EMF drops below the value set by the
SDTHR bits in the STALL register. A programmable counter circuit allows the assertion of the STALLn output to
be delayed until the back EMF has been sampled below the SDTHR value for more than one zero-current step.
The counter is programmed by the SDCNT bits in the STALL register, and provides selections of 1, 2, 4, or 8
steps.
When the stall is detected (at the end of a SMPLTH interval), the STALLn/BEMFVn pin is driven active low, and
the STD bit and the STDLAT bit in the STATUS register are set. The STALLn/BEMFVn pin will deassert and the
STD bit will automatically clear at the next zero-current step if a stall condition is not detected, while the STDLAT
bit will remain set until a '0' is written to it. The STDLAT is reset when the STD bit clears after the first zero-cross
step that does not detect a stall condition.
This stall detection scheme is only effective when the motor is stalled while running at or above some minimum
speed. Since it relies on detecting a drop in motor back EMF, the motor must be rotating with sufficient speed to
generate a detectable back EMF. During motor start-up, and at very slow step rates, the stall detection is not
reliable.
Since back EMF can only be sampled during a zero-current state, stall detection is not possible in full step mode.
During full-step operation, the stall detect circuit is gated off to prevent false signaling of a stall.
The correct setting of the SDTHR bits needs to be determined experimentally. It is dependent on many factors,
including the electrical and mechanical characteristics of the load, the peak current setting, and the supply
voltage.
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