BQ4822Y Datasheet, PDF (3/16 Pages) Texas Instruments – RTC Module With 8Kx8 NVSRAM

bq4822Y
Address Map
The bq4822Y provides 16 bytes of clock and control
status registers and 8,176 bytes of storage RAM.
Figure 2 illustrates the address map for the bq4822Y.
Table 1 is a map of the bq4822Y registers, and Table 2
describes the register bits.
Memory Interface
Read Mode
The bq4822Y is in read mode whenever OE (output en-
able) is low and CE (chip enable) is low. The device ar-
chitecture allows ripple-through access of data from
eight of 65,536 locations in the static storage array.
Thus, the unique address specified by the 13 address in-
puts defines which one of the 8,192 bytes of data is to be
accessed. Valid data is available at the data I/O pins
within tAA (address access time) after the last address
input signal is stable, providing that the CE and OE
(output enable) access times are also satisfied. If the CE
and OE access times are not met, valid data is available
after the latter of chip enable access time (tACE) or out-
put enable access time (tOE).
CE and OE control the state of the eight three--state data
I/O signals. If the outputs are activated before tAA, the data
lines are driven to an indeterminate state until tAA. If the
address inputs are changed while CE and OE remain low,
output data remains valid for tOH (output data hold time),
but goes indeterminate until the next address access.
Write Mode
The bq4822Y is in write mode whenever WE and CE are
active. The start of a write is referenced from the
latter--occurring falling edge of WE or CE. A write is
terminated by the earlier rising edge of WE or CE. The
addresses must be held valid throughout the cycle. CE
or WE must return high for a minimum of tWR2 from
CE or tWR1 from WE prior to the initiation of another
read or write cycle.
Data-in must be valid tDW prior to the end of write and
remain valid for tDH1 or tDH2 afterward. OE should be
kept high during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a low on
CE and OE, a low on WE disables the outputs tWZ after
WE falls.
16 Bytes
Clock and ^1FFF
Control Status _1FF0
Registers
1FEF
8,176
Bytes
Storage
RAM
0000
0
Year
1FFF
1
Month
1FFE
2
Date
1FFD
3
Days
1FFC
4
Hours
1FFB
5
Minutes
1FFA
6
Seconds 1FF9
7
Control
1FF8
8 Watchdog 1FF7
9 Interrupts 1FF6
10 Alarm Date 1FF5
11 Alarm Hours 1FF4
12 Alarm Minutes 1FF3
13 Alarm Seconds 1FF2
Tenths/
14 _Hundredths 1FF1
15
Flags
1FF0
FG482201.eps
May 1997
Figure 2. Address Map
3