BQ4822Y Datasheet, PDF (12/16 Pages) Texas Instruments – RTC Module With 8Kx8 NVSRAM

bq4822Y
Write Cycle (TA =TOPR _, VCCMIN ≤ VCC ≤ VCCMAX)
Symbol
tWC
tCW
tAW
Parameter
Write cycle time
Chip enable to end of write
Address valid to end of write
tAS
Address setup time
tWP
Write pulse width
tWR1
Write recovery time (write cycle 1)
tWR2
Write recovery time (write cycle 2)
tDW
Data valid to end of write
tDH1
Data hold time (write cycle 1)
tDH2
tWZ
tOW
Data hold time (write cycle 2)
Write enabled to output in high Z
Output active from end of write
–70
Min. Max.
70
-
55
-
60
-
0
-
50
-
0
-
0
-
30
-
5
-
5
-
0
25
5
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions/Notes
(1)
(1)
Measured from address valid to be-
ginning of write. (2)
Measured from beginning of write
to end of write. (1)
Measured from WE going high to
end of write cycle. (3)
Measured from CE going high to
end of write cycle. (3)
Measured to first low-to-high tran-
sition of either CE or WE.
Measured from WE going high to
end of write cycle. (4)
Measured from CE going high to
end of write cycle. (4)
I/O pins are in output state. (5)
I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
May 1997
12