BQ24158_12 Datasheet, PDF (3/45 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger

www.ti.com
A1
VBUS
bq24153A, bq24156A
bq24158, bq24159
SLUSAB0A – OCTOBER 2010 – REVISED FEBRUARY 2012
PIN LAYOUT (20-Bump YFF Package)
bq24153A/8
bq24156A/9
(Top View)
(Top View)
A2
A3
A4
VBUS
BOOT
SCL
A1
A2
A3
A4
VBUS
VBUS
BOOT
SCL
B1
PMID
B2
PMID
C1
C2
SW
SW
B3
PMID
C3
SW
B4
SDA
C4
STAT
B1
PMID
C1
SW
B2
PMID
C2
SW
B3
PMID
C3
SW
B4
SDA
C4
STAT
D1
PGND
E1
CSIN
D2
PGND
E2
CD
D3
PGND
D4
OTG
E3
VREF
E4
CSOUT
D1
PGND
E1
CSIN
D2
PGND
E2
CD
D3
PGND
D4
SLRST
E3
VREF
E4
CSOUT
NAME
CSOUT
VBUS
PMID
SW
BOOT
PGND
CSIN
SCL
SDA
STAT
VREF
CD
PIN
NO.
E4
A1, A2
B1, B2, B3
C1, C2, C3
A3
D1, D2, D3
E1
A4
B4
C4
E3
E2
OTG
(bq24153A/8 only)
D4
SLRST
(bq24156A/9 only)
D4
PIN FUNCTIONS
I/O
DESCRIPTION
I
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 μF) to PGND if
there are long inductive leads to battery.
I/O
Charger input voltage. Bypass it with a 1-μF ceramic capacitor from VBUS to PGND. It also provides power
to the load during boost mode (bq24153A/8 only) .
I/O
Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of
3.3-μF capacitor from PMID to PGND.
O Internal switch to output inductor connection.
I/O
Bootstrap capacitor connection for the high-side FET gate driver. Connect a 10-nF ceramic capacitor (voltage
rating ≥ 10 V) from BOOT pin to SW pin.
Power ground
I
Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-μF ceramic
capacitor to PGND is required.
I I²C interface clock. Connect a 10-kΩ pullup resistor to 1.8V rail (V_AUX= V_{CC_HOST})
I/O I²C interface data. Connect a 10-kΩ pullup resistor to 1.8V rail (V_AUX= V_{CC_HOST})
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128-μs
O pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to
drive a LED or communicate with a host processor.
O
Internal bias regulator voltage. Connect a 1µF ceramic capacitor from this output to PGND. External load on
VREF is not recommended.
Charge disable control pin. CD=0, charge is enabled. CD=1, charge is disabled and VBUS pin is high
I impedance to GND. In 15min mode, Setting CD=1 resets the 15min timer; while in 32s mode, Setting CD=1
will NOT reset the 32-second timer.
Boost mode enable control or input current limiting selection pin. When OTG is in active status, bq24153A/8
is forced to operate in boost mode. It has higher priority over I²C control and can be disabled using the
I control register. At POR while in 15-min mode, the OTG pin is default to be used as the input current limiting
selection pin. The I²C register is ignored at startup. When OTG=High, I_{IN_LIMIT}=500mA and when OTG=Low,
I_{IN_LIMIT}=100mA.
Safety limit register reset control. When SLRST=0, bq24156A/9 resets all the safety limits (06H) to default
I values, regardless of the write actions to safety limits registers (06H). When SLRST=1, bq24156A/9 can
program the safety limit register until any write action to other registers locks the programmed safety limits.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): bq24153A bq24156A bq24158 bq24159