BQ24158_12 Datasheet, PDF (24/45 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger

bq24153A, bq24156A
bq24158, bq24159
SLUSAB0A – OCTOBER 2010 – REVISED FEBRUARY 2012
www.ti.com
STAT Pin in Boost Mode
During normal boosting operation, the STAT pin behaves as a high impedance (open-drain) output. Under fault
conditions, a 128-μs pulse is sent out to notify the host.
HIGH IMPEDANCE (Hi-Z) MODE
In Hi-Z mode, the charger stops charging and enters a low quiescent current state to conserve power. Taking the
CD pin high causes the charger to enter Hi-Z mode. When in 15-minute mode and the CD pin is low, the charger
automatically enters Hi-Z mode if
1. VBUS > UVLO and a battery with V_BAT > V_LOWV is inserted, or
2. VBUS falls below UVLO.
Taking the CD pin high while in 15-minute mode resets the 15 minute timer.
When in HOST mode and the CD is low, the charger can be placed into Hi-Z mode if the HZ-MODE control bit is
set to “1” and OTG pin is not in active status. Once the bq24153A/6A/8/9 enters Hi-Z mode and the CD pin is
low, a low power 32-second timer is enabled when the battery voltage is below V_(LOWV) to monitor if the host
control is available or not. If the low power 32-second timer expires, the IC operates in 15-minute mode and the
low power 32 second timer is disabled.
In order to exit Hi-Z mode, the CD pin must be low, VBUS must be higher than UVLO and the HOST must write
a "0" to the HZ-MODE control bit.
SERIAL INTERFACE DESCRIPTION
I²C is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I²C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The IC works as a slave and is compatible with the following data transfer modes, as defined in the I²C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write
mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements. Register contents remain intact as long as
supply voltage remains above 2.2 V (typical). I²C is asynchronous, which means that it runs off of SCL. The
device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is recommended that
SDA changes while SCL is LOW.
The data transfer protocol for standard and fast modes is the same; therefore, they are referred to as F/S-mode
in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as
HS-mode. The bq24153A/6A/8/9 device supports 7-bit addressing only. The device 7-bit address is defined as
‘1101011’ (6BH) for bq24153A, and ‘1101010’ (6AH) for bq24156A/8/9.
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 31. All I²C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 31. START and STOP Condition
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