BQ24158_12 Datasheet, PDF (25/45 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger

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bq24153A, bq24156A
bq24158, bq24159
SLUSAB0A – OCTOBER 2010 – REVISED FEBRUARY 2012
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 32). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 32) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 32. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 34). This releases the bus and stops the communication
link with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to
prevent the slave I²C logic from getting stuck in a bad state. Attempting to read data from register addresses not
listed in this section will result in FFh being read out.
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
START
Condition
Not Acknowledge
Acknowledge
1
2
8
Figure 33. Acknowledge on the I²C Bus™
9
Clock Pulse for
Acknowledgement
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