TMS320C6672_15 Datasheet, PDF (229/238 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS708E—March 2014
Added note to DDR3 PLL initialization sequence (Page 151)
Corrected MPU0 Memory Protection End Address from 0x026203FF to 0x026207FF (Page 184)
Revised IPCGRH register description (Page 86)
Corrected DDR3 transfer rate from 1033 MTS to 1066 MTS (Page 197)
Added CVDD and SmartReflex voltage parameter in SmartReflex switching table (Page 125)
Removed DDR3 PLL initialization sequence from data manual to PLL controller user guide (Page 151)
Removed PASS PLL initialization sequence from data manual to PLL controller user guide (Page 154)
Updated chip select from CS[5:2] to CE[3:0] in EMIF16 Peripheral section (Page 215)
Updated EMIF chip select from CS[5:2] to CE[3:0] in Memory Map Summary table (Page 23)
Updated DDR3 PLL initialization sequence (Page 152)
Added footnote for DDR3 EMIF data in memory map summary table (Page 23)
Updated Tracer descriptions across the data manual (Page 17)
Corrected PASSCLK(N/P) max cycle time from 6.4 ns to 25 ns (Page 155)
Updated the Timer numbering across the whole document (Page 18)
Corrected PASS PLL clock to SRIOSGMIICLK in the boot device values table for Ethernet. (Page 25)
Added clarification for RESETSTATz input current (Page 115)
Added note for VCNTLID register that it is available for debug purpose only (Page 128)
Added STM Trace Switching Characteristics table (Page 225)
Removed the incorrect description of 16-Bit EMIF in Features section (Page 1)
Updated th(MDCLKH-MDIO) value from 10 ns to 0 ns in MDIO Timing Requirements table (Page 220)
Updated the description of NAND in the footnote of memory map summary table (Page 23)
Updated tw(DPnH) and tw(DPnL) descriptions in Trace Switching Characteristics tables (Page 225)
Updated I2C master mode table that bits[9:8] are used for mode selection (Page 28)
Updated the I2C passive mode table that bits[9:8] are used for mode selection and actual value on the bus is 0x19+bits[7:5] (Page 29)
Updated I2C data rate configuration descriptions in I2C Master Mode Configuration table (Page 28)
Added PLLSELECT bit to PASSPLLCTL1 Register (Page 154)
Added SPI device-specific support details (Page 204)
Corrected that only the sticky bits in PCIe MMRs will be retained after soft reset (Page 133)
Revision C
Added note stating that both SGMII ports can be used for boot (Page 27)
Updated the DDR3 MMR descriptions and deleted the unrelated PCIe MMR descriptions for soft reset. (Page 133)
Corrected physical 36-bit addresses of DDR3 EMIF configuration/data (Page 23)
Added TeraNet connection figures and added bridge numbers to the connection tables. (Page 96)
Restricted Output Divide of SECCTL register to max value of divide by 2 (Page 141)
Updated DEVSPEED register for both silicon rev1.0 and 2.0 (Page 93)
Removed RESETFULLz parameter from 4b timing description (Page 121)
Added supported data rates for HyperLink (Page 207)
Changed chip level interrupt controller name from INTC to CIC (Page 162)
Changed TPCC to EDMA3CC and TPTC to EDMA3TC (Page 156)
Added PLLRST bit to DDR3PLLCTL1 register (Page 151)
Added PLLRST bit to PASSPLLCTL1 register (Page 154)
Deleted INTC0 register map address offset 0x4 and 0x8, which are Reserved (Page 176)
Corrected the SGMII SerDes clock to PASS clock in PASS PLL configuration description (Page 38)
Corrected PASS PLL clock from SRIOSGMIICLK to PASSCLK in the boot device values table for Ethernet. (Page 25)
Corrected the SPI and DDR3/HyperLink Config end addressed (Page 23)
Added the DDR3 PLL Initialization Sequence (Page 151)
Added the Main PLL and PLL Controller Initialization Sequence (Page 148)
Added the PASS PLL Initialization Sequence (Page 154)
Added HyperLink interrupt event section (Page 207)
Added events #144-159 to INTC2 event input table (Page 170)
Added DEVSPEED Register section. (Page 93)
Added more description to Boot Sequence section (Page 23)
Corrected a typo, changed DDRCLKN to DDRCLKP (Page 152)
Copyright 2014 Texas Instruments Incorporated
Revision History 229