TMS320C6672_15 Datasheet, PDF (157/238 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708E—March 2014
• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
7.9.1 EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant
addressing mode is applicable to a very limited set of use cases. For most applications, increment mode must be used.
For more information on these two addressing modes, see the Enhanced Direct Memory Access 3 (EDMA3)
Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.
For the range of memory addresses that include EDMA3 channel controller (EDMA3CC) control registers and
EDMA3 transfer controller (EDMA3TC) control register see Section Table 2-2‘‘Memory Map Summary’’ on
page 17. For memory offsets and other details on EDMA3CC and EDMA3TC control registers entries, see the
Enhanced Direct Memory Access 3 (EDMA3) Controller for KeyStone Devices User Guide in ‘‘Related Documentation
from Texas Instruments’’ on page 72.
7.9.2 EDMA3 Channel Controller Configuration
Table 7-33 shows the configuration for each of the EDMA3 channel controllers present on the device.
Table 7-33 EDMA3 Channel Controller Configuration
Description
Number of DMA channels in Channel Controller
Number of QDMA channels
Number of interrupt channels
Number of PaRAM set entries
Number of event queues
Number of Transfer Controllers
Memory Protection Existence
Number of Memory Protection and Shadow Regions
End of Table 7-33
EDMA3 CC0
16
8
16
128
2
2
Yes
8
EDMA3 CC1
64
8
64
512
4
4
Yes
8
EDMA3 CC2
64
8
64
512
4
4
Yes
8
7.9.3 EDMA3 Transfer Controller Configuration
Each transfer controller on a device is designed differently based on considerations like performance requirements,
system topology (like main TeraNet bus width, external memory bus width), etc. The parameters that determine the
transfer controller configurations are:
• FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight data.
The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored
and subsequently written out to the destination endpoint by the TC write controller.
• BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main TeraNet interface.
• Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued by a
transfer controller.
• DSTREGDEPTH: This determines the number of destination FIFO register set. The number of destination
FIFO register set for a transfer controller determines the maximum number of outstanding transfer requests.
All four parameters listed above are fixed by the design of the device.
Table 7-34 shows the configuration for each of the EDMA3 transfer controllers present on the device.
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