TMS320C6672_15 Datasheet, PDF (108/238 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708E—March 2014
5.1.3 L2 Memory
The L2 memory configuration for the C6672 device is as follows:
• Total memory size is 4096KB
• Each core contains 512KB of memory
• Local starting address for each core is 0080 0000h
L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2
memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register
(L2CFG) of the C66x CorePac. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is
configured as all SRAM after device reset.
Figure 5-4 L2 Memory Configurations
L2 Mode Bits
000
001
010
011
100
101
L2 Memory
Block Base
Address
0080 0000h
ALL
15/16
7/8
3/4
1/2
ALL
SRAM SRAM SRAM SRAM SRAM Cache
256Kbytes
4-Way
Cache
0084 0000h
128Kbytes
4-Way
Cache
4-Way
Cache
4-Way
Cache
4-Way
Cache
64Kbytes
32Kbytes
32Kbytes
0086 0000h
0087 0000h
0087 8000h
0087 FFFFh
Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by
the associated processor through aliased addresses, where the eight MSBs are masked to 0. The aliasing is handled
within the C66x CorePac and allows for common code to be run unmodified on multiple cores. For example, address
location 0x10800000 is the global base address for C66x CorePac Core 0's L2 memory. C66x CorePac Core 0 can
access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000
only. Conversely, 0x00800000 can by used by any of the cores as their own L2 base addresses.
For C66x CorePac Core 0, as mentioned, this is equivalent to 0x10800000 and for C66x CorePac Core 1 this is
equivalent to 0x11800000. Local addresses should be used only for shared code or data, allowing a single image to
be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run-time by
a particular core should always use the global address only.
108 C66x CorePac
Copyright 2014 Texas Instruments Incorporated
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