TMS320C6672_15 Datasheet, PDF (114/238 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708E—March 2014
6.2 Recommended Operating Conditions
Table 6-2
Recommended Operating Conditions ^{(1) (2)}
CVDD
SR core supply
Initial Startup
1000MHz - Device
1250MHz - Device
Min
VINITnom × 0.95
SRVnom ⁽⁴⁾× 0.95
SRVnom × 0.95
Nom
1.1 ⁽³⁾
0.85-1.1
0.9-1.1
Max Unit
VINITnom × 1.05
SRVnom × 1.05
V
SRVnom × 1.05
1500MHz - Device
SRVnom × 0.95
0.9-1.1
SRVnom × 1.05
CVDD1
Core supply voltage for memory array
DVDD18 1.8-V supply I/O voltage
DVDD15 1.5-V supply I/O voltage
VREFSSTL
V_DDRx ⁽⁵⁾
V_DDAx
V_DDTx
V_SS
V_IH
DDR3 reference voltage
SerDes regulator supply
PLL analog supply
SerDes termination supply
Ground
High-level input voltage
LVCMOS (1.8 V)
I²C
DDR3 EMIF
LVCMOS (1.8 V)
V_IL
Low-level input voltage
DDR3 EMIF
I²C
Commercial
T_C
Operating case temperature
Extended
End of Table 6-2
0.95
1.71
1.425
0.49 × DVDD15
1.425
1.71
0.95
0
0.65 × DVDD18
0.7 × DVDD18
VREFSSTL + 0.1
-0.3
0
-40
1
1.8
1.5
0.5 × DVDD15
1.5
1.8
1
0
1.05 V
1.89 V
1.575 V
0.51 × DVDD15 V
1.575 V
1.89 V
1.05 V
0V
V
V
V
0.35 × DVDD18 V
VREFSSTL - 0.1 V
0.3 × DVDD18 V
85 °C
100 °C
1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SerDes I/Os comply with the XAUI Electrical Specification, IEEE
802.3ae-2002.
2 All SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
3 The initial CVDD voltage at power on will be 1.1V nominal and it must transition to VID set value immediately after being presented on VCNTL pins. This is required to maintain
full power functionality and reliability targets guaranteed by TI.
4 SRVnom refers to the unique SmartReflex core supply voltage set from the factory for each individual device.
5 Where x = 1, 2, 3, 4... to indicate all supplies of the same kind.
114 Device Operating Conditions
Copyright 2014 Texas Instruments Incorporated
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