TL16C451 Datasheet, PDF (18/23 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENTS

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053C – MAY 1989 – REVISED AUGUST 1999
PRINCIPLES OF OPERATION
Iine control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and are described in the following bulleted list.
D Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 5.
Table 5. Serial Character Word Length
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Word Length
5 bits
6 bits
7 bits
8 bits
D Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The number of stop bits generated in relation
to word length and bit 2 is as shown in Table 6.
Table 6. Number of Stop Bits Generated
Bit 2
Word Length Selected
by Bits 1 and 2
Number of Stop
Bits Generated
0
Any word length
1
5 bits
1
6 bits
1
7 bits
1
8 bits
1
1 1/2
2
2
2
D Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked. When bit
3 is cleared, no parity is generated or checked.
D Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic is in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared,
odd parity (an odd number of logic 1s) is selected.
D Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.
D Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition, i.e, a condition where SOUT
terminal is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled. The
break condition has no affect on the transmitter logic, it only affects the serial output.
D Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.
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