TL16C451 Datasheet, PDF (15/23 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENTS

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053C – MAY 1989 – REVISED AUGUST 1999
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers are given in Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
O DLAB = 0 O DLAB = 0 1 DLAB = 0
2
3
4
5
6
7
O DLAB = 1 1 DLAB = 1
Bit
Receiver Transmitter
Interrupt
No.
Buffer
Register
(Read
Holding
Register
(Write
Interrupt
Enable
Register
Ident.
Register
(Read
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Modem
Status
Register
Scratch
Register
Divisor
Latch
(LSB)
Only)
Only)
Only)
Latch
(MSB)
RBR
THR
IER
IIR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
Enable
Word
0
Data Bit 0† Data Bit 0
Received
Data
Available
Interrupt
“0” If
Interrupt
Pending
Length
Select
Bit 0
(WLSO)
Data
Terminal
Ready
(DTR)
Data
Ready
(DR)
Delta
Clear
to Send
(DCTS)
Bit 0
(ERBF)
Bit 0
Bit 8
Enable
Transmitter
Word
Delta
Holding
Interrupt Length Request Overrun
Data
1
Data Bit 1 Data Bit 1
Register
ID
Select
to Send
Error
Set
Bit 1
Empty
Bit (0)
Bit 1
(RTS)
(OE)
Ready
Interrupt
(WLS1)
(DDSR)
(ETBE)
Bit 1
Bit 9
Enable
2
Data Bit 2
Data Bit 2
Receiver
Line Status
Interrupt
(ELSI)
Interrupt
ID
Bit (1)
Number of
Stop Bits
(STB)
Out 1
Parity
Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
Enable
Modem
3
Data Bit 3 Data Bit 3
Status
Interrupt
(EDSSI)
Delta
0
Parity
Enable
(PEN)
Out 2
(Interrupt
Enable)
Framing
Error
(FE)
Receive
Line
Signal
Detect
Bit 3
(DRLSD)
Bit 3
Bit 11
4
Data Bit 4 Data Bit 4
0
0
Even
Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear
to
Send
(CTS)
Bit 4
Bit 4
Bit 12
5
Data Bit 5 Data Bit 5
0
0
Stick
Parity
0
Transmit-
ter
Holding
Register
Data
Set
Ready
Bit 5
Bit 5
(THRE)
(DSR)
Bit 13
6
Data Bit 6 Data Bit 6
0
Transmit-
0
Set
Break
ter
Ring
0
Empty ^Indicator
Bit 6
(RI)
Bit 6
(TEMT)
Bit 14
Divisor
Receive
Latch
Line
7
Data Bit 7 Data Bit 7
0
0
Access
0
0
Signal
Bit 7
Bit 7
Bit
Detect
(DLAB)
(RLSD)
† _{Bit 0 is the least significant bit. It is the first bit serially transmitted or received.}
Bit 15
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