TL16C451 Datasheet, PDF (14/23 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENTS

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053C – MAY 1989 – REVISED AUGUST 1999
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB† A2
A1
A0
REGISTER
0
L
L
L Receiver buffer (read), transmitter holding register (write)
0
L
L
H Interrupt enable register
X
L
H
L Interrupt identification register (read only)
X
L
H
H Line control register
X
H
L
L Modem control register
X
H
L
H Line status register
X
H
H
L Modem status register
X
H
H
H Scratch register
1
L
L
L Divisor latch (LSB)
1
L
L
H Divisor latch (MSB)
† _{The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB}
signal is controlled by writing to this bit location (see Table 3).
Table 2. ACE Reset Functions
REGISTER/SIGNAL
Interrupt enable register
Interrupt identification register
Line control register
Modem control register
Line status register
Modem status register
SOUT
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
INTRPT (modem status changes)
OUT2 (interrupt enable)
RTS
DTR
OUT1
Scratch register
Divisor latch (LSB and MSB) registers
Receiver buffer registers
Transmitter holding registers
RESET
CONTROL
RESET STATE
RESET
All bits cleared (0 – 3 forced and 4 – 7 permanent)
RESET
Bit 0 is set, bits 1 and 2 are cleared, and bits 3 – 7
are permanently cleared
RESET
All bits cleared
RESET
All bits cleared
RESET
Bits 5 and 6 are set, all other bits are cleared
RESET
Bits 0 – 3 are cleared, bits 4 – 7 are input signals
RESET
High
Read LSR/RESET Low
Read RBR/RESET Low
Read IIR/Write
THR/RESET
Low
Read MSR/RESET Low
RESET
High
RESET
High
RESET
High
RESET
High
RESET
No effect
RESET
No effect
RESET
No effect
RESET
No effect
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