TL16C451 Datasheet, PDF (17/23 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENTS

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053C – MAY 1989 – REVISED AUGUST 1999
PRINCIPLES OF OPERATION
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most microprocessors.
The ACE provides four prioritized levels of interrupts:
D Priority 1 – Receiver line status (highest priority)
D Priority 2 – Receiver data ready or receiver character time out
D Priority 3 – Transmitter holding register empty
D Priority 4 – Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and indicates the type of interrupt
in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and
described in Table 4.
D Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When this bit is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.
D Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 4.
D Bits 3 – 7: These bits in the interrupt identification register are not used and are always clear.
INTERRUPT
IDENTIFICATION
REGISTER
BIT 2
BIT 1
BIT 0
0
0
1
1
1
0
1
0
0
0
1
0
0
0
0
Table 4. Interrupt Control Functions
PRIORITY
LEVEL
INTERRUPT TYPE
None
None
1
Receiver line status
2
Received data available
INTERRUPT SOURCE
None
Overrun error, parity error,
framing error or break
interrupt
Receiver data available
3
Transmitter holding register Transmitter holding register
empty
empty
4
Modem status
Clear to send, data set
ready, ring indicator, or data
carrier detect
INTERRUPT RESET
METHOD
–
Reading the line status
register
Reading the receiver buffer
register
Reading the interrupt
Identification register (if
source of interrupt) or writing
into the transmitter holding
register
Reading the modem status
register
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