TL16C451 Datasheet, PDF (16/23 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENTS

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053C – MAY 1989 – REVISED AUGUST 1999
PRINCIPLES OF OPERATION
interrupt control logic
The interrupt control logic is shown in Figure 10.
DR (LSR Bit 0)
ERBFI (IER Bit 0)
THRE (LSR bit 5)
ETBEI (IER Bit 1)
OE (LSR bit 1)
PE (LSR Bit 2)
FE (LSR bit 3)
BI (LSR Bit 4)
ELSI (IER Bit 1)
DCTS (MSR Bit 0)
DDSR (MSR Bit 1)
Interrupt
Output
TERI (MSR Bit 2)
DRLSD (MSR Bit 3)
EDSSI (IER Bit 3)
INTERRUPT ENABLE (MCR Bit 3)
Figure 10. Interrupt Control Logic
interrupt enable register (IER)
The IER enables each of the four types of interrupts (refer to Table 4) and the INTRPT output signal in response
to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The
contents of this register are summarized in Table 3 and are described in the following bulleted list.
D Bit 0: This bit, when set, enables the received data available interrupt.
D Bit 1: This bit, when set, enables the THRE interrupt.
D Bit 2: This bit, when set, enables the receiver line status interrupt.
D Bit 3: This bit, when set, enables the modem status interrupt.
D Bits 4 thru 7: These bits in the IER are not used and are always cleared.
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