LM3489_15 Datasheet, PDF (17/25 Pages) Texas Instruments – Hysteretic PFET Buck Controller With Enable Pin

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LM3489
LM3489-Q1
SNVS443B – MAY 2006 – REVISED FEBRUARY 2013
PCB Layout
The PCB board layout is very important in all switching regulator designs. Poor layout can cause switching noise
into the feedback signal and generate EMI problems. For minimal inductance, the wires indicated by heavy lines
in schematic diagram should be as wide and short as possible. Keep the ground pin of the input capacitor as
close as possible to the anode of the catch diode. This path carries a large AC current. The switching node, the
node with the diode cathode, inductor and FET drain should be kept short. This node is one of the main sources
for radiated EMI since it sees a large AC voltage at the switching frequency. It is always a good practice to use a
ground plane in the design, particularly for high current applications.
The two ground pins, PGND and GND, should be connected by as short a trace as possible. They can be
connected underneath the device. These pins are resistively connected internally by approximately 50Ω. The
ground pins should be tied to the ground plane, or to a large ground trace in close proximity to both the FB
divider and C_OUT grounds.
The gate pin of the external PFET should be located close to the PGATE pin. However, if a very small FET is
used, a resistor may be required between PGATE pin and the gate of the PFET to reduce high frequency ringing.
Since this resistor will slow down the PFET’s rise time, the current limit blanking time should be taken into
consideration (refer to Current Limiting Operation). The feedback voltage signal line can be sensitive to noise.
Avoid inductive coupling with the inductor or the switching node. The FB trace should be kept away from those
areas. Also, the orientation of the inductor can contribute un-wanted noise coupling to the FB path. If noise
problems are observed it may be worth trying a different orientation of the inductor and select the best for final
component placement.
V_IN
7V ± 35V
C_ADJ R_ADJ
1 nF 24k
Q1 FDC5614P
C_{IN1 +}
22 PF
50V
C_IN2
0.1 PF
50V
R_IS
270
7
PGATE
1
ISENSE
5
8
ADJ
VIN
LM3489
FB
GND
4
2
3
EN PGND
SD*
6
* Short to shutdown
the device
L 22 PH
V_OUT
3.3V/0.5A
MBRS140
D1
C_ff
100 pF
R1
33k _{+ COUT}
100 PF
6.3V
R2
20k
Figure 30. Typical Application Schematic for VOUT = 3.3V/500mA
Copyright © 2006–2013, Texas Instruments Incorporated
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