LM3489_15 Datasheet, PDF (15/25 Pages) Texas Instruments – Hysteretic PFET Buck Controller With Enable Pin

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LM3489
LM3489-Q1
SNVS443B – MAY 2006 – REVISED FEBRUARY 2013
OUTPUT CAPACITOR SELECTION (C_OUT)
The ESR of the output capacitor times the inductor ripple current is equal to the output ripple of the regulator.
However, the V_HYST sets the first order value of this ripple. As ESR is increased with a given inductance,
operating frequency increases as well. If ESR is reduced then the operating frequency reduces.
The use of ceramic capacitors has become a common desire of many power supply designers. However,
ceramic capacitors have a very low ESR resulting in a 90° phase shift of the output voltage ripple. This results in
low operating frequency and increased output ripple. To fix this problem a low value resistor should be added in
series with the ceramic output capacitor. Although counter intuitive, this combination of a ceramic capacitor and
external series resistance provides highly accurate control over the output voltage ripple. Other types capacitor,
such as Sanyo POS CAP and OS-CON, Panasonic SP CAP, and Nichicon "NA" series, are also recommended
and may be used without additional series resistance.
For all practical purposes, any type of output capacitor may be used with proper circuit verification.
INPUT CAPACITOR SELECTION (C_IN)
A bypass capacitor is required between the input source and ground. It must be located near the source pin of
the external PFET. The input capacitor prevents large voltage transients at the input and provides the
instantaneous current when the PFET turns on.
The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the
manufacturer's recommended voltage derating. For high input voltage applications, low ESR electrolytic,
Nichicon "UD" series or the Panasonic "FK" series are available. The RMS current in the input capacitor can be
calculated as follows:
I_{RMS_CIN} = I_OUT x
V_OUT(V_IN ± V_OUT)
V_IN
(12)
The input capacitor power dissipation can be calculated as follows.
P_D(CIN) = I_{RMS_CIN2} x ESR_CIN
(13)
The input capacitor must be able to handle the RMS current and the dissipation. Several input capacitors may be
connected in parallel to handle large RMS currents. In some cases it may be much cheaper to use multiple
electrolytic capacitors than a single low ESR, high performance capacitor such as OS-CON or Tantalum. The
capacitance value should be selected such that the ripple voltage created by the switch current pulses is less
than 10% of the total DC voltage across the capacitor.
For high VIN conditions (> 28V), the fast switching, high swing of the internal gate drive introduces unwanted
disturbance to the VIN rail and the current limit function can be affected. In order to eliminate this potential
problem, a high quality ceramic capacitor of 0.1 µF is recommended to filter out the internal disturbance at the
VIN pin. This capacitor should be placed right next to the VIN pin for best performance.
PROGRAMMING THE CURRENT LIMIT (R_ADJ)
The current limit is determined by connecting a resistor (R_ADJ) between input voltage and the ADJ pin, pin 5.
R_ADJ
= I_{IND_PEAK} x
R_DSON
I_{CL_ADJ}
(14)
where:
R_DSON : Drain-Source ON resistance of the external PFET
I_{CL_ADJ} : 3.0µA minimum
I_{IND_PEAK} = I_LOAD + I_RIPPLE/2
Using the minimum value for I_{CL_ADJ} (3.0µA) ensures that the current limit threshold will be set higher than the
peak inductor current.
The R_ADJ value must be selected to ensure that the voltage at the ADJ pin does not fall below 3.5V. With this in
mind, R_{ADJ_MAX} = (V_IN-3.5)/7µA. If a larger R_ADJ value is needed to set the desired current limit, either use a
PFET with a lower R_DSON, or use a current sense resistor as shown in Figure 28.
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