LM3489_15 Datasheet, PDF (13/25 Pages) Texas Instruments – Hysteretic PFET Buck Controller With Enable Pin

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LM3489
LM3489-Q1
SNVS443B – MAY 2006 – REVISED FEBRUARY 2013
Figure 28. Current Sensing by External Resistor
PGATE
When switching, the PGATE pin swings from VIN (off) to some voltage below VIN (on). How far the PGATE will
swing depends on several factors including the capacitance, on time, and input voltage.
PGATE voltage swing will increase with decreasing gate capacitance. Although PGATE voltage will typically be
around VIN-5V, with very small gate capacitances, this value can increase to a typical maximum of VIN-8.3V.
Additionally, PGATE swing voltage will increase as on time increases. During long on times, such as when
operating at 100% duty cycle, the PGATE voltage will eventually fall to its maximum voltage of VIN-8.3V (typical)
regardless of the PFET gate capacitance.
The PGATE voltage will not fall below 0.4V (typical). Therefore, when the input voltage falls below approximately
9V, the PGATE swing voltage range will be reduced. At an input voltage of 7V, for instance, PGATE will swing
from 7V to a minimum of 0.4V.
DEVICE ENABLE, SHUTDOWN
The LM3489 can be remotely shutdown by forcing the enable pin to ground. With EN pin grounded, the internal
blocks other than the enable logic are de-activated and the shutdown current of the device will be lowered to only
7µA (typical). Releasing the EN pin allows for normal operation to resume. The EN pin is internally pulled high
with the voltage clamped at 8V typical. For normal operation this pin should be left open. In case an external
voltage source is applied to this pin for enable control, the applied voltage should not exceed the maximum
operating voltage level specified in this datasheet, i.e. 5.5V.
ADJUSTABLE UVLO
The under-voltage-lockout function can be implemented as shown in Figure 29. By incorporating the feature of
the internal enable threshold, the lockout level can be programmed through an external potential divider formed
with R3 and R4. The input voltage information is detected and compared with the enable threshold and the
device operation will be inhibited when V_IN drops below the preset UVLO level. The UVLO and hysteresis voltage
can be calculated as follows:
V_IN(UVLO) = V_{EN 1 +} ^R4
R3
(7)
V_{IN(UVLO_HYST)} = V_{EN_HYST} x
1+
R4
R3
(8)
where V_EN is the enable rising threshold voltage and V_{EN_HYST} is the enable threshold hysteresis.
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