LM3489_15 Datasheet, PDF (16/25 Pages) Texas Instruments – Hysteretic PFET Buck Controller With Enable Pin

LM3489
LM3489-Q1
SNVS443B – MAY 2006 – REVISED FEBRUARY 2013
The current limit function can be disabled by connecting the ADJ pin to ground and ISENSE to VIN.
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CATCH DIODE SELECTION (D1)
The important parameters for the catch diode are the peak current, the peak reverse voltage, and the average
power dissipation. The average current through the diode can be calculated as following.
I_{D_AVE} = I_OUT x (1 − D)
(15)
The off state voltage across the catch diode is approximately equal to the input voltage. The peak reverse
voltage rating must be greater than input voltage. In nearly all cases a Schottky diode is recommended. In low
output voltage applications a low forward voltage provides improved efficiency. For high temperature
applications, diode leakage current may become significant and require a higher reverse voltage rating to
achieve acceptable performance.
P-CHANNEL MOSFET SELECTION (Q1)
The important parameters for the PFET are the maximum Drain-Source voltage (V_DS), the on resistance (R_DSON),
Current rating, and the input capacitance.
The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward
voltage. The V_DS must be selected to provide some margin beyond the input voltage.
PFET drain current, Id, must be rated higher than the peak inductor current, I_IND-PEAK.
Depending on operating conditions, the PGATE voltage may fall as low as V_IN - 8.3V. Therefore, a PFET must
be selected with a V_GS maximum rating greater than the maximum PGATE swing voltage.
As input voltage decreases below 9V, PGATE swing voltage may also decrease. At 5.0V input the PGATE will
swing from V_IN to V_IN - 4.6V. To ensure that the PFET turns on quickly and completely, a low threshold PFET
should be used when the input voltage is less than 7V.
Total power loss in the FET can be approximated using the following equation:
PD_switch = R_DSON x I_OUT2x D + F x I_OUT x V_IN x (t_on + t_off)/2
(16)
where:
t_on = FET turn on time
t_off = FET turn off time
A value of 10ns to 20ns is typical for ton and toff.
A PFET should be selected with a turn on rise time of less than 100ns. Slower rise times will degrade efficiency,
can cause false current limiting, and in extreme cases may cause abnormal spiking at the PGATE pin.
The R_DSON is used in determining the current limit resistor value, R_ADJ. Note that the R_DSON has a positive
temperature coefficient. At 100°C, the R_DSON may be as much as 150% higher than the 25°C value. This
increase in R_DSON must be considered when determining R_ADJ in wide temperature range applications. If the
current limit is set based upon 25°C ratings, then false current limiting can occur at high temperature.
Keeping the gate capacitance below 2000pF is recommended to keep switching losses and transition times low.
This will also help keep the PFET drive current low, which will improve efficiency and lower the power dissipation
within the controller.
As gate capacitance increases, operating frequency should be reduced and as gate capacitance decreases
operating frequency can be increased.
INTERFACING WITH THE ENABLE PIN
The enable pin is internally pulled high with clamping at 8V typical. For normal operation this pin should be left
open. To disable the device, the enable pin should be connected to ground externally. If an external voltage
source is applied to this pin for enable control, the applied voltage should not exceed the maximum operating
voltage level specified in this datasheet, i.e. 5.5V. For most applications, an open drain or open collector
transistor can be used to short this pin to ground to shutdown the device .
16
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