LM3489_15 Datasheet, PDF (11/25 Pages) Texas Instruments – Hysteretic PFET Buck Controller With Enable Pin

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LM3489
LM3489-Q1
SNVS443B – MAY 2006 – REVISED FEBRUARY 2013
140
L=22PH
120
L=10PH
100
80
60
L=4.7PH
40
20
0
0 5 10 15 20 25 30 35
INPUT VOLTAGE - OUTPUT VOLTAGE (V)
Figure 25. Propagation Delay
The operating frequency and output ripple voltage can also be significantly influenced by the speed up capacitor
(Cff). Cff is connected in parallel with the high side feedback resistor, R1. The location of this capacitor is similar
to where a phase lead capacitor would be located in a PWM control scheme. However it's effect on hysteretic
operation is much different. Cff effectively shorts out R1 at the switching frequency and applies the full output
ripple to the FB pin without dividing by the R2/R1 ratio. The end result is a reduction in output ripple and an
increase in operating frequency. When adding Cff, calculate the formula above with α = 1. The value of Cff
depend on the desired operating frequency and the value of R2. A good starting point is 470pF ceramic at
100kHz decreasing linearly with increased operating frequency. Also note that as the output voltage is
programmed below 2.5V, the effect of Cff will decrease significantly.
CURRENT LIMIT OPERATION
The LM3489 has a cycle-by-cycle current limit. Current limit is sensed across the V_DS of the PFET or across an
additional sense resistor. When current limit is activated, the LM3489 turns off the external PFET for a period of
9µs(typical). The current limit is adjusted by an external resistor, R_ADJ.
The current limit circuit is composed of the ISENSE comparator and the one-shot pulse generator. The positive
input of the ISENSE comparator is the ADJ pin. An internal 5.5µA current sink creates a voltage across the
external R_ADJ resistor. This voltage is compared to the voltage across the PFET or sense resistor. The ADJ
voltage can be calculated as follows:
V_ADJ = V_IN − (R_ADJ x 3.0µA)
(5)
Where 3.0µA is the minimum I_CL-ADJ value.
The negative input of the ISENSE comparator is the ISENSE pin that should be connected to the drain of the
external PFET. The inductor current is determined by sensing the V_DS. It can be calculated as follows.
V_ISENSE = V_IN − (R_DSON x I_{IND_PEAK}) = V_IN − V_DS
(6)
Figure 26. Current Sensing by V_DS
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