AM1707_15 Datasheet, PDF (167/200 Pages) Texas Instruments – AM1707 ARM® Microprocessor

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AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
Table 6-96. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 0530
0x01E0 0532
0x01E0 0534
0x01E0 0536
0x01E0 0538
0x01E0 053A
0x01E0 053B
0x01E0 053C
0x01E0 053D
0x01E0 0540
0x01E0 0542
0x01E0 0544
0x01E0 0546
0x01E0 0548
0x01E0 054A
0x01E0 054B
0x01E0 054C
0x01E0 054D
0x01E0 1000
0x01E0 1004
0x01E0 1008
0x01E0 1800
0x01E0 1808
0x01E0 180C
0x01E0 1810
0x01E0 1820
0x01E0 1828
0x01E0 182C
0x01E0 1830
ACRONYM
REGISTER DESCRIPTION
CONTROL AND STATUS REGISTER FOR ENDPOINT 3
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for
the host Transmit endpoint.
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for
the host Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 4
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for
the host Transmit endpoint.
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for
the host Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host Receive endpoint.
DMA REGISTERS
DMAREVID
DMA Revision Register
TDFDQ
DMA Teardown Free Descriptor Queue Control Register
DMAEMU
DMA Emulation Control Register
TXGCR[0]
Transmit Channel 0 Global Configuration Register
RXGCR[0]
Receive Channel 0 Global Configuration Register
RXHPCRA[0]
Receive Channel 0 Host Packet Configuration Register A
RXHPCRB[0]
Receive Channel 0 Host Packet Configuration Register B
TXGCR[1]
Transmit Channel 1 Global Configuration Register
RXGCR[1]
Receive Channel 1 Global Configuration Register
RXHPCRA[1]
Receive Channel 1 Host Packet Configuration Register A
RXHPCRB[1]
Receive Channel 1 Host Packet Configuration Register B
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Peripheral Information and Electrical Specifications 167
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