AM1707_15 Datasheet, PDF (101/200 Pages) Texas Instruments – AM1707 ARM® Microprocessor

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AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
6.16.2 McASP Electrical Data/Timing
6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-47 and Table 6-48 assume testing over recommended operating conditions (see Figure 6-34 and
Figure 6-35).
Table 6-47. McASP0 Timing Requirements^{(1) (2)}
No.
PARAMETER
1 t_c(AHCLKRX)
Cycle time, AHCLKR0 external, AHCLKR0 input
Cycle time, AHCLKX0 external, AHCLKX0 input
2 t_w(AHCLKRX)
Pulse duration, AHCLKR0 external, AHCLKR0 input
Pulse duration, AHCLKX0 external, AHCLKX0 input
3 t_c(ACLKRX)
Cycle time, ACLKR0 external, ACLKR0 input
Cycle time, ACLKX0 external, ACLKX0 input
4 t_w(ACLKRX)
Pulse duration, ACLKR0 external, ACLKR0 input
Pulse duration, ACLKX0 external, ACLKX0 input
Setup time, AFSR0 input to ACLKR0 internal⁽³⁾
Setup time, AFSX0 input to ACLKX0 internal
Setup time, AFSR0 input to ACLKR0 external input⁽³⁾
5 t_{su(AFSRX-ACLKRX) Setup time, AFSX0 input to ACLKX0 external input}
Setup time, AFSR0 input to ACLKR0 external output⁽³⁾
Setup time, AFSX0 input to ACLKX0 external output
Hold time, AFSR0 input after ACLKR0 internal⁽³⁾
Hold time, AFSX0 input after ACLKX0 internal
Hold time, AFSR0 input after ACLKR0 external input⁽³⁾
6 t_{h(ACLKRX-AFSRX) Hold time, AFSX0 input after ACLKX0 external input}
Hold time, AFSR0 input after ACLKR0 external output⁽³⁾
7
t_{su(AXR-ACLKRX)}
8
t_{h(ACLKRX-AXR)}
Hold time, AFSX0 input after ACLKX0 external output
Setup time, AXR0[n] input to ACLKR0 internal ⁽³⁾
Setup time, AXR0[n] input to ACLKX0 internal⁽⁴⁾
Setup time, AXR0[n] input to ACLKR0 external input⁽³⁾
Setup time, AXR0[n] input to ACLKX0 external input ⁽⁴⁾
Setup time, AXR0[n] input to ACLKR0 external output⁽³⁾
Setup time, AXR0[n] input to ACLKX0 external output ⁽⁴⁾
Hold time, AXR0[n] input after ACLKR0 internal⁽³⁾
Hold time, AXR0[n] input after ACLKX0 internal⁽⁴⁾
Hold time, AXR0[n] input after ACLKR0 external input⁽³⁾
Hold time, AXR0[n] input after ACLKX0 external input ⁽⁴⁾
Hold time, AXR0[n] input after ACLKR0 external output⁽³⁾
Hold time, AXR0[n] input after ACLKX0 external output ⁽⁴⁾
MIN
25
25
12.5
12.5
greater of 2P or 25
greater of 2P or 25
12.5
12.5
9.4
9.4
2.9
2.9
2.9
2.9
-1.2
-1.2
0.9
0.9
0.9
0.9
9.4
9.4
2.9
2.9
2.9
2.9
-1.3
-1.3
0.5
0.5
0.5
0.5
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(4) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
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