AM1707_15 Datasheet, PDF (116/200 Pages) Texas Instruments – AM1707 ARM® Microprocessor

AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
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Table 6-59. Additional⁽¹⁾ SPI0 Slave Timings, 4-Pin Enable Option^{(2) (3)}
No.
PARAMETER
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Delay from final
24
t_{d(SPC_ENAH)S}
SPI0_CLK edge to
slave deasserting
SPI0_ENA.
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
MIN
1.5 P - 3
MAX
UNIT
2.5 P + 18.5
– 0.5t_c(SPC)M + 1.5 P - 3 – 0.5t_c(SPC)M + 2.5 P + 18.5
ns
1.5 P - 3
2.5 P + 18.5
– 0.5t_c(SPC)M + 1.5 P - 3 – 0.5t_c(SPC)M + 2.5 P + 18.5
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-55).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-60. Additional⁽¹⁾ SPI0 Slave Timings, 4-Pin Chip Select Option^{(2) (3)}
No.
25 t_{d(SCSL_SPC)S}
26 t_{d(SPC_SCSH)S}
27 t_{ena(SCSL_SOMI)S}
28 t_{dis(SCSH_SOMI)S}
PARAMETER
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Required delay from final
SPI0_CLK edge before
SPI0_SCS is deasserted.
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
MIN
2P
0.5t_c(SPC)M + P + 5
P+5
0.5t_c(SPC)M + P + 5
P+5
MAX
UNIT
ns
ns
P + 18.5 ns
P + 18.5 ns
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-55).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
116 Peripheral Information and Electrical Specifications
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