AM1707_15 Datasheet, PDF (108/200 Pages) Texas Instruments – AM1707 ARM® Microprocessor

AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
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Table 6-52. McASP2 Switching Characteristics⁽¹⁾
No.
9 t_c(AHCLKRX)
10 t_w(AHCLKRX)
11 t_c(ACLKRX)
12 t_w(ACLKRX)
13 t_{d(ACLKRX-AFSRX)}
14 t_{d(ACLKX-AXRV)}
15 t_{dis(ACLKX-AXRHZ)}
PARAMETER
Cycle time, AHCLKR2 internal, AHCLKR2 output
Cycle time, AHCLKR2 external, AHCLKR2 output
Cycle time, AHCLKX2 internal, AHCLKX2 output
Cycle time, AHCLKX2 external, AHCLKX2 output
Pulse duration, AHCLKR2 internal, AHCLKR2 output
Pulse duration, AHCLKR2 external, AHCLKR2 output
Pulse duration, AHCLKX2 internal, AHCLKX2 output
Pulse duration, AHCLKX2 external, AHCLKX2 output
Cycle time, ACLKR2 internal, ACLKR2 output
Cycle time, ACLKR2 external, ACLKR2 output
Cycle time, ACLKX2 internal, ACLKX2 output
Cycle time, ACLKX2 external, ACLKX2 output
Pulse duration, ACLKR2 internal, ACLKR2 output
Pulse duration, ACLKR2 external, ACLKR2 output
Pulse duration, ACLKX2 internal, ACLKX2 output
Pulse duration, ACLKX2 external, ACLKX2 output
Delay time, ACLKR2 internal, AFSR output⁽⁷⁾
Delay time, ACLKX2 internal, AFSX output
Delay time, ACLKR2 external input, AFSR output ⁽⁷⁾
Delay time, ACLKX2 external input, AFSX output
Delay time, ACLKR2 external output, AFSR output ⁽⁷⁾
Delay time, ACLKX2 external output, AFSX output
Delay time, ACLKX2 internal, AXR2[n] output
Delay time, ACLKX2 external input, AXR2[n] output
Delay time, ACLKX2 external output, AXR2[n] output
Disable time, ACLKX2 internal, AXR2[n] output
Disable time, ACLKX2 external input, AXR2[n] output
Disable time, ACLKX2 external output, AXR2[n] output
MIN
15
15
15
15
(AHR/2) – 2.5⁽²⁾
(AHR/2) – 2.5⁽²⁾
(AHX/2) – 2.5⁽³⁾
(AHX/2) – 2.5⁽³⁾
greater of 2P or 15 ns⁽⁴⁾
greater of 2P or 15 ns⁽⁴⁾
greater of 2P or 15 ns⁽⁴⁾
greater of 2P or 15 ns⁽⁴⁾
(AR/2) – 2.5⁽⁵⁾
(AR/2) – 2.5⁽⁵⁾
(AX/2) – 2.5⁽⁶⁾
(AX/2) – 2.5⁽⁶⁾
-1.4
-1.4
2.1
2.1
2.1
2.1
-1.4
2.1
2.1
-1.4
2.9
2.9
(1) McASP2 ACLKX2 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP2 ACLKX2 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP2 ACLKX2 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP2 ACLKR2 internal – ACLKR2CTL.CLKRM = 1, PDIR.ACLKR =1
McASP2 ACLKR2 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP2 ACLKR2 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR2.
(3) AHX - Cycle time, AHCLKX2.
(4) P = SYSCLK2 period
(5) AR - ACLKR2 period.
(6) AX - ACLKX2 period.
(7) McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2
MAX
2.8
2.8
10
10
10
10
2.8
10
10
2.8
10
10
UNIT
ns
ns
ns
ns
ns
ns
ns
108 Peripheral Information and Electrical Specifications
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