AM1707_15 Datasheet, PDF (122/200 Pages) Texas Instruments – AM1707 ARM® Microprocessor

AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
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Table 6-69. Additional⁽¹⁾ SPI1 Slave Timings, 5-Pin Option^{(2) (3)}
No.
25 t_{d(SCSL_SPC)S}
26 t_{d(SPC_SCSH)S}
27 t_{ena(SCSL_SOMI)S}
28 t_{dis(SCSH_SOMI)S}
29 t_{ena(SCSL_ENA)S}
30 t_{dis(SPC_ENA)S}
PARAMETER
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Required delay from final SPI1_CLK
edge before SPI1_SCS is
deasserted.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
Delay from master deasserting SPI1_SCS to slave driving
SPI1_ENA valid
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Delay from final clock receive edge
on SPI1_CLK to slave 3-stating or
driving high SPI1_ENA.⁽⁴⁾
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
MIN
2P
0.5t_c(SPC)M + P +
5
P+5
0.5t_c(SPC)M + P +
5
P+5
MAX
UNIT
ns
ns
P + 19 ns
P + 19 ns
19 ns
2.5 P + 19
2.5 P + 19
ns
2.5 P + 19
2.5 P + 19
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-63).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is 3-
stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
122 Peripheral Information and Electrical Specifications
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