THCV217_16 Datasheet, PDF (9/35 Pages) THine Electronics, Inc. – V-by-One HS High-speed Video Data Transmitter and Receiver

Functional Description
Functional Overview
With V-by-One^®HS’s proprietary encoding scheme and CDR (Clock and Data Recovery) architecture,
THCV217 and THCV218 enable transmission of 8/10 bit RGB, 2bits of user-defined data (CONT),
synchronizing signals HSYNC, VSYNC, and DE by single/dual differential pair cable with minimal external
components.
THCV217, the transmitter, inputs CMOS data (including video data, CONT, HSYNC, VSYNC, and DE) and
serializes video data and synchronizing signals separately, depending on the polarity of DE. DE is a signal which
indicates whether video or synchronizing data are active. When DE is high, it serializes video data inputs into
differential data streams. And it transmits serialized synchronizing data when DE is low.
Figure 1 is the conceptual diagram of the basic operation of the chipset.
THCV218, the receiver, automatically extracts the clock from the incoming data streams and converts the serial
data into video data with DE being high or synchronizing data with DE being low, recognizing which type of
serial data is being sent by the transmitter. And it outputs the recovered data in the form of CMOS data.
THCV218 can operate for a wide range of a serial bit rate from 600Mbps to 3.4Gbps/channel.
Figure 2 shows the timing diagram of the basic operation of the chipset.
It does not need any external frequency reference, such as a crystal oscillator.
Data Enable
There are some requirements for DE signal as described in Figure 1, Figure 2, and Table 18.
If DE=Low, control data of same cycle and possibly particular assigned data bit ‘CTL’ except the first and the
last pixel are transmitted. Otherwise video data are transmitted during DE=High.
Control data from receiver in DE=High period are previous data of DE transition. See Figure 2.
The length of DE being low and high is at least 2 clock cycles long, as described in Table 18.
Data Enable must be toggled like High -> Low -> High at regular interval.
CTL bit transmission
There are particular assigned data bit ‘CTL’ which can be transmitted both on DE=High and on DE=Low
except the first and the last pixel on DE=Low.
This function is enabled by setting THCV218 Reserved7 pin to High.
THCV217
Data bit : R/G/B, CONT
H
Control bit : V,HSYNC
Data bit : CTL*
L
DE
THCV218
R/G/B,
CONT,
CTL
DE=H, R/G/B,CONT
DE=L, CTL* except the 1st and the last pixel
other R/G/B,CONT=Low Fixed
DE=H, V,HSYNC=Fixed
DE=L, V,HSYNC
V,HSYNC
DE
*CTL are particular assigned bit among R/G/B, CONT that can carry arbitrary data during DE=Low period.
*CTL bit transmission is activated by setting THCV218 Reserved7 pin to High.
Figure 1. Conceptual diagram of the basic operation of the chipset
THCV217-THCV218_Rev.2.11_E
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