THCV217_16 Datasheet, PDF (1/35 Pages) THine Electronics, Inc. – V-by-One HS High-speed Video Data Transmitter and Receiver

THCV217 and THCV218
V-by-One^® HS High-speed Video Data Transmitter and Receiver
General Description
THCV217 and THCV218 are designed to support
video data transmission between the host and display.
One high-speed lane can carry up to 32bit data and 3
bits of synchronizing signals at a pixel clock
frequency from 20MHz to 85MHz.
The chipset, which has two high-speed data lanes,
can transmit video data up to 1080p/10b/60Hz. The
maximum serial data rate is 3.4Gbps/lane.
Features
 Color depth selectable: 24(8×3)/32(10×3)bit
 Single-in/Single-out, Single-in/Dual-out, and
Dual-in/Dual-out selectable for THCV217
 Single-in/Single-out, Dual-in/Single-out, and
Dual-in/Dual-out selectable for THCV218
 AC coupling for high-speed lines
 CORE 1.8V, CMOS IO 3.3V
 Package: 217(TFBGA105), 218(TFBGA145)
 Wide frequency range
 CDR requires no external frequency reference
 Spread Spectrum Clocking tolerant
Up to 30kHz / ±0.5% (center spread)
 V-by-One® HS standard Version1.4 compliant.
Product
Link
Pixel Clock
Frequency
THCV217 Si/So 20MHz to 85MHz
Di/Do
Si/Do 40MHz to 170MHz
THCV218 Si/So 20MHz to 85MHz
Di/Do
Di/So 40MHz to 170MHz
Si/So: Single-in/Single-out, Di/Do: Dual-in/Dual-out
Di/So: Dual-in/Single-out, Si/Do: Single-in/Dual-out
Block Diagram
R1[9:0]
G1[9:0]
B1[9:0]
CONT1[2:1]
CMOS
R2[9:0]
G2[9:0]
B2[9:0]
CONT2[2:1]
HSYNC
VSYNC
DE
CLKIN
MODE
DEMUX
COL
BET
PRE
R/F
PDN
THCV217
Controls
TX0p
TX0n
RX0p
RX0n
CML
TX1p
TX1n
RX1p
RX1n
Open
Drain
HTPDN
LOCKN
HTPDN
LOCKN
DGLOCK
THCV218
Controls
R1[9:0]
G1[9:0]
B1[9:0]
CONT1[2:1]
CMOS
R2[9:0]
G2[9:0]
B2[9:0]
CONT2[2:1]
HSYNC
VSYNC
DE
CLKOUT
MODE1,0
COL
PLL
BET
R/F
DKEN,DK
PDN,OE
BETOUT
THCV217-THCV218_Rev.2.11_E
1
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