THCV217_16 Datasheet, PDF (8/35 Pages) THine Electronics, Inc. – V-by-One HS High-speed Video Data Transmitter and Receiver

THCV218 Pin Description (Continued)
PIN Name
Ball #
Type*
Description
PLL bandwidth select
PLL
K1
I3 H: CLKIN<40MHz, when SiSo,DiDo
L: Normal Operation
Output enable input (See Table 1 for details)
OE
L2
I3 H: All CMOS outputs enabled
L: All CMOS outputs disabled, except for LOCKN, HTPDN
DGLOCK
N1
I3PU
Connect all DGLOCK pins in multiple-chip configuration.
Must be left OPEN for single-chip configuration.
Output clock triggering edge select input
R/F
M1
I3 H: Rising edge
L: Falling edge
DK enable
DKEN
L4
I3 H: DK enabled
L: DK disabled (Default)
Output clock delay timing select input. Enabled by DKEN.
DK
K3
I3
H: Late
L: Early
Refer to Figure 10 for details.
BETOUT
E1
Reserved7
G2
Reserved3
D3
O3 Field BET result output. Must be left OPEN when NOT used.
CTL bit transmission on DE=low blanking period enable
I3
H: CTL bit enabled (CTL are transmitted except the 1st and the last pixel of DE=Low)
L: CTL bit disabled (CTL are Low fixed during DE=Low)
When BET=High, Reserved7 must be Low.
O3 Reserved outputs. Must be left OPEN.
Reserved1,
4-6
VDL
CAVDL
C4,C3,E2,G1
C5,C6,L5,L6
E3,F3,G3,H3,J3
I3 Reserved input. Must be tied to GND
P 1.8V power supply pins for digital circuitry
P 1.8V power supply pins for CML inputs and PLL circuitry
DVDH
C7,C8,C9,C10,C11,
D11,E11,F11,F12,
H11,J11,K11,L7,
L8,L9,L10,L11
P3 3.3V power supply pins for TTL outputs
GND
E5,E6,E7,E8,E9,F5,
F6,F7,F8,F9,G5,G6,
G7,G8,G9,G11, GND Ground pins
G12,H5,H6,H7,H8,
H9,J5,J6,J7,J8,J9
*type symbol
CI=CML Input, OD3=3.3V Open drain output, O3=3.3V CMOS output
I3=3.3V CMOS input, I3L=Low speed 3.3V CMOS input, I3PU=3.3V CMOS inout with an on-chip pullup resistor
P=1.8V power supply, P3=3.3V power supply
PDN
L
L
H
H
OE
R/G/B/CONT
H,Vsync,DE,CLKOUT
L
Hi-Z
H
All Low
L
Hi-Z
H
Data Out
Table 1. Output Control
THCV217-THCV218_Rev.2.11_E
8
Copyright(C)2016 THine Electronics,Inc.
THine Electronics, Inc.
Security E