THCV215_16 Datasheet, PDF (7/26 Pages) THine Electronics, Inc. – V-by-One HS High-speed Video Data Transmitter and Receiver

LVDS Mapping
LVDS data (video data, Hsync, Vsync, DE) are mapped as Figure 4. TLC0[6] is special bit for DE(data enable),
and TLC0[5:4] are for Hsync, Vsync data bits and the other bits are for video data.
The number of LVDS channel depends on color depth mode(COL[1:0]).
If SDSEL=Low, only channel 0 (Figure 4, n=0) is active. If SDSEL=High, both channel 0/1(Figure 4, n=0/1) are
active. (TLC1[6:4] are not available).
Depending on color mode, TLD1[6] and TLD0[6] are not available. See Table 3.
Vdiff = (TLCLKn +) - (TLCLKn-)
n=0,1
Vdiff=0V
tTCIP
Color depth
12,10, 8, 6
previous cycle
current cycle
next cycle
TLAn +/-
TLAn1 TLAn0 TLAn6 TLAn5 TLAn4 TLAn3 TLAn2 TLAn1 TLAn0 TLAn6 TLAn5 TLAn4 TLAn3 TLAn2 TLAn1
TLBn +/-
TLBn1 TLBn0 TLBn6 TLBn5 TLBn4 TLBn3 TLBn2 TLBn1 TLBn0 TLBn6 TLBn5 TLBn4 TLBn3 TLBn2 TLBn1
TLCn +/-
TLDn +/-
TLCn1
TLCn0
TLCn6
(DE)
TLCn5
(V)
TLCn4
(H)
TLCn3
TLCn2
TLCn1
TLCn0
TLCn6
(DE)
TLCn5
(V)
TLCn4
(H)
TLCn3
TLCn2
TLCn1
TLDn1 TLDn0 TLDn6 TLDn5 TLDn4 TLDn3 TLDn2 TLDn1 TLDn0 TLDn6 TLDn5 TLDn4 TLDn3 TLDn2 TLDn1
TLEn +/-
TLEn1 TLEn0 TLEn6 TLEn5 TLEn4 TLEn3 TLEn2 TLEn1 TLEn0 TLEn6 TLEn5 TLEn4 TLEn3 TLEn2 TLEn1
TLFn +/-
TLFn1 TLFn0 TLFn6 TLFn5 TLFn4 TLFn3 TLFn2 TLFn1 TLFn0 TLFn6 TLFn5 TLFn4 TLFn3 TLFn2 TLFn1
Data Enable Control data bit
Figure 4. LVDS mapping timing diagram
THCV215-216_Rev.2.70_E
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