THCV215_16 Datasheet, PDF (4/26 Pages) THine Electronics, Inc. – V-by-One HS High-speed Video Data Transmitter and Receiver

Pin Description
THCV215
Pin Name Pin #
TX0 +/- 50,51
TX1 +/- 47,48
TLA0+/- 4,3
TLB0+/- 6,5
TLC0+/- 8,7
TLCLK0+/- 10,9
TLD0+/- 12,11
TLE0+/- 14,13
TLF0+/- 16,15
TLA1+/- 18,17
TLB1+/- 20,19
TLC1+/- 22,21
TLCLK1+/- 24,23
TLD1+/- 26,25
TLE1+/- 28,27
TLF1+/- 30,29
LOCKN
56
HTPDN
57
PDN
58
COL1,
COL0
61,60
SDSEL
62
Type* Description
CO
CO CML Data Output
LI
LI
LI
LI
LI
LI
LI
LI
LI
LI
LI
LI
LI
LI LVDS Data Input
I Lock detect input
I Hot plug detect input
Power down input
H: Normal Operation
L: Power down (CML output High Fix,
I other High-Z)
Color depth select input
L,L: 6bit
L,H: 8bit
H,L: 10bit
I H,H: 12bit
Single/Dual select input
L: Channel0 enable, Channel1 disable
I H: Channel0, Channel1 enable
DRV1
42
I Must be tied to GND
DRV0
41
I Must be tied to VDL
PRE1,
PRE0
40,39
RDY
59
Reserved1 37
Reserved0 38
Pre-emphasis level select input
L,L: 0%
H,L: 100%
L,H: not available
I H,H: not available
Link status ready output
L: not ready
O H: ready
Field BET mode enable input
L: Normal operation (default)
I H: Field BET mode enabled
I Must be tied to GND
VDL
35,55 P 1.8V power supply pin for digital circuitry
GND
CAVDL
CAGND
CPVDL
CPGND
LPVDL
LPGND
LAVDH
LAGND
36,54
45,53
46,49,52
43
44
33,64
34,63
2,31
1,32
P Ground pin for digital circuitry
P 1.8V power supply pin for CML output
P Ground pin for CML output
P 1.8V power supply pin for PLL circuitry
P Ground pin for PLL circuitry
P 1.8V power supply pin for LVDS PLL
P Ground pin for LVDS PLL circuitry
P 3.3V power supply pin for LVDS input
P Ground pin for LVDS input
Note) All CMOS inputs are 1.8V-inputs
except for THCV216's RS
THCV216
Pin Name Pin #
RX0 +/- 15,14
RX1 +/- 19,18
RLA0+/- 61,62
RLB0+/- 59,60
RLC0+/- 57,58
RLCLK0+/ 55,56
RLD0+/- 53,54
RLE0+/- 51,52
RLF0+/- 49,50
RLA1+/- 47,48
RLB1+/- 45,46
RLC1+/- 43,44
RLCLK1+/ 41,42
RLD1+/- 39,40
RLE1+/- 37,38
RLF1+/- 35,36
LOCKN
7
HTPDN
6
Type* Description
CI
CI CML Data Input
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO LVDS Data Output
O Lock detect output (open drain)
O Hot plug detect output (open drain)
PDN
COL1,
COL0
SDSEL
RS
Power down input
H: Normal Operation
27
I L: Power down (High-Z)
Color depth select input
L,L: 6bit
L,H: 8bit
H,L: 10bit
4,5
I H,H: 12bit
Single/Dual select input
L: Channel0 enable, Channel1 disable
3
I H: Channel0, Channel1 enable
Direction of RS pin depends on
Reserved3.
LVDS swing range select input
30 IO3 ^{when Reserved3=L}
H: Normal swing (350mV typ.)
L: Reduced swing (200mV typ.)
Field BET output when Reserved3=H.
Goes LOW when errors detected.
Reserved
1,2
26,28 I Must be tied to GND
Field BET mode enable input
L: Normal operation (default)
Reserved3 29
I H: Field BET mode enabled
VDL
8,25 P 1.8V power supply pin for digital circuitry
GND
9,24 P Ground pin for digital circuitry
CAVDL 12,21 P 1.8V power supply pin for CML input
13,16,
CAGND 17,20 P Ground pin for CML input
CPVDL0 10
P 1.8V power supply pin for PLL circuitry
CPGND0 11
P Ground pin for PLL circuitry
CPVDL1 23
P 1.8V power supply pin for PLL circuitry
CPGND1 22
P Ground pin for PLL circuitry
LPVDH 1,32 P 3.3V power supply pin for LVDS PLL
LPGND 2,31 P Ground pin for LVDS PLL circuitry
LAVDH 34,63 P 3.3V power supply pin for LVDS output
LAGND 33,64 P Ground pin for LVDS output
*type symbol
I=1.8V CMOS Input, O=1.8V CMOS Output, IO3=3.3V CMOS I/O
LI=LVDS Input, LO= LVDS Output
CI=CML Input, CO=CML Output
P=Power
THCV215-216_Rev.2.70_E
Copyright(C)2016 THine Electronics, Inc.
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