THCV215_16 Datasheet, PDF (5/26 Pages) THine Electronics, Inc. – V-by-One HS High-speed Video Data Transmitter and Receiver

Functional Description
Functional Overview
With V-by-One^®HS’s proprietary encoding scheme and CDR (Clock and Data Recovery) architecture, THCV215
and THCV216 enable transmission of 18/24/30/36bits per pixel video data (Rn/Gn/Bn/CONTn), Hsync
(HSYNCn), Vsync (VSYNCn) data and Data Enable (DE) by single/dual differential pair cable with minimal
external components.
THCV215, the transmitter, inputs LVDS data (including video data, Hsync, Vsync and DE) and serializes video
data and Hsync, Vsync data separately, depending on the polarity of DE. DE is a signal which indicates whether
video or Hsync, Vsync data are active. When DE is high, it serializes video data inputs into a single differential
data stream. And it transmits serialized Hsync, Vsync data when DE is low.
THCV216, the receiver, automatically extracts the clock from the incoming data stream and converts the serial
data into video data with DE being high or Hsync, Vsync data with DE being low, recognizing which type of
serial data is being sent by the transmitter. And it outputs the recovered data in the form of LVDS data.
THCV216 can seamlessly operate for a wide range of a serial bit rate from 600Mbps to 3.75Gbps/channel,
detecting the frequency of an incoming data stream, and recovering both the clock and data by itself.
It does not need any external frequency reference, such as a crystal oscillator.
Data Enable Requirement (DE)
There are some requirements for DE as described in Figure 2, Figure 3 and Table 15.
Dual LVDS input to THCV215 should be synchronized in terms of DE transition. See Figure 2.
If DE=Low, Hsync and Vsync data of same cycle are transmitted. Otherwise video data of that are transmitted
(DE=High). SYNC data from receiver in DE=High period are previous data of DE transition. See Figure 3.
The length of DE being low and high is at least 2 clock cycles long as described in Table 15.
Data Enable must be toggled like High -> Low -> High at regular interval.
THCV 215
THCV 216
Rn/Gn/Bn ^D[39:0]
CONTn
H
D[39:0]
H
Rn/Gn/Bn
CONTn
Hsync
HSYNCn
VSYNCn
Vsync
L
DE
Hsync
Vsync
L
DE
HSYNCn
VSYNCn
Figure 1. Conceptual diagram of the basic operation of the chipset
Vdiff = (TLCLK0+) – (TLCLK0-)
DE
DE
DE
DE
DE
DE
Vdiff = (TLC0+) – (TLC0-)
Vdiff = (TLCLK1+) – (TLCLK1-)
DE
DE
DE
DE
DE
DE
Vdiff = (TLC1+) – (TLC1-)
Figure 2. Service condition of DE input synchronization
THCV215-216_Rev.2.70_E
Copyright(C)2016 THine Electronics, Inc.
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THine Electronics, Inc.
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