THCV215_16 Datasheet, PDF (12/26 Pages) THine Electronics, Inc. – V-by-One HS High-speed Video Data Transmitter and Receiver

Field BET Operation
In order to help users to check the validity of high speed serial links (CML lines), THCV215/THCV216 have
an operation mode in which they act as the bit error tester (BET). In this mode, THCV215 internally generates a
test pattern, which is then serialized onto the CML high speed lines. THCV216 receives the data stream and
checks the sampled data for bit errors.
This "Field BET" mode is activated by setting Reserved1= H on THCV215 and Reserved3= H on THCV216
(Refer to Table 5).
In the Field BET mode, the on-chip pattern generator on THCV215 is enabled and generates the test pattern as
long as the LVDS clocks (TLCLK0+/-, TLCLK1+/-) are applied. Other LVDS data inputs may be left open or
applied with any pattern. They are ignored by THCV215. The generated data pattern is then 8b/10b encoded,
scrambled, and serialized onto the CML channels. As for THCV216, the internal test pattern check circuit gets
enabled and the RS pin, which is normally an input, turns into an output for the pattern checker (LVDS output
level is internally configured to be "Normal Swing”). The RS pin goes LOW whenever bit errors occur, and it
stays HIGH when there is no bit error. Please Refer to Figure 8.
Product
Pin Name
Normal
Field BET
THCV215
THCV216
Reserved1 Reserved3
RS
L
L
3.3V INPUT
H: Normal Swing, L: Reduced Swing
H
H
3.3V OUTPUT
Goes LOW when bit errors occur.
Table 5. Field BET Operation Pin Settings
LVDS data inputs
are ignored
THCV215
LVDS clock to
TLCLK0, 1
Test Pattern
Generator
Reserved1=H
(Field BET mode)
THCV216
Test
Pattern
Checker
Reserved3=H
(Field BET mode)
LVDS Swing Select
for
Normal Operation
R
S
Test Point
for
Field BET
Figure 8. Field BET Configuration
THCV215-216_Rev.2.70_E
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