THCV215_16 Datasheet, PDF (16/26 Pages) THine Electronics, Inc. – V-by-One HS High-speed Video Data Transmitter and Receiver

Switching Characteristics
Symbol
Parameter
tDEH
DE=High Duration
tDEL
DE=Low Duration
Conditions
Min.
2tTCIP
2tTCIP
Typ.
-
-
Table 15. DE requirement
Max.
-
-
Units
sec
sec
Symbol
tTCIP
tTCIH
tTCIL
tSK
tTIP1
tTIP0
tTIP6
tTIP5
tTIP4
tTIP3
tTIP2
tTISK
tTRF
tTOSK
tTCD
tTPD
tTPLL0
tTPLL1
tTNP0
tTNP1
Parameter
Conditions
Min.
Typ.
Max.
Units
COL[1:0]=L,L | L,H
10
-
50
ns
COL[1:0]=H,L
11.76
-
50
ns
TLCLK Period
COL[1:0]=H,H
13.3
-
50
ns
LVDS Differential Clock High Time
2×tTCIP/7
-
5×tTCIP/7
ns
LVDS Differential Clock Low Time
2×tTCIP/7
-
5×tTCIP/7
ns
tTCIP=75MHz
-440
-
440
ps
tTCIP=85MHz
-390
-
390
ps
LVDS Receiver Skew Margin
tTCIP=100MHz
-330
-
330
ps
LVDS Input Data Position0
-tSK
0
+tSK
ns
LVDS Input Data Position1
LVDS Input Data Position2
LVDS Input Data Position3
LVDS Input Data Position4
LVDS Input Data Position5
LVDS Input Data Position6
Lane0/1 LVDS Input Clock Skew
tTCIP/7-tSK
tTCIP/7
tTCIP/7+tSK ns
2×tTCIP/7-tSK 2×tTCIP/7 2×tTCIP/7+tSK ns
3×tTCIP/7-tSK 3×tTCIP/7 3×tTCIP/7+tSK ns
4×tTCIP/7-tSK 4×tTCIP/7 4×tTCIP/7+tSK ns
5×tTCIP/7-tSK 5×tTCIP/7 5×tTCIP/7+tSK ns
6×tTCIP/7-tSK 6×tTCIP/7 6×tTCIP/7+tSK ns
-0.3×tTCIP
-
0.3×tTCIP
ns
CML Output Rise and Fall Time(20%-80%)
50
-
150
ps
CML Lane0/1 Output Inter Pair Skew
Input Clock to Output Data Delay
-2
-
2
UI
(56/(5×n)+6.1)
(56/(5×n)+6.1)
×tTCIP-5 (1)
-
×tTCIP+5 (1) ns
Power On to PDN High Delay
0
-
-
ns
PDN High to CML Output Delay
-
-
10
ms
PDN Low to CML Output High Fix Delay
LOCKN High to Training Pattern Output
-
-
20
ns
Delay
LOCKN Low to Data Pattern Output
-
-
10
ms
Delay
-
-
10
ms
(1) n =3, 4, and 5 for 6/8bit, 10bit, and 12bit mode, respectively.
Table 16. THCV215 Switching Characteristics
Symbol
tRBIT
tRISK
tRLVT
tROP1
tROP0
tROP6
tROP5
tROP4
tROP3
tROP2
tROSK
tRDC
tRPD
tRHPD0
tRHPD1
tRPLL0
tRPLL1
tRLCK0
tRLCK1
Parameter
Conditions
Min.
Typ.
Max.
Units
COL[1:0]=L,L | L,H
333
tTCIP/30
1667
ps
COL[1:0]=H,L
294
tTCIP/40
1250
ps
Unit Interval
COL[1:0]=H,H
266
tTCIP/50
1000
ps
CML Lane0/1 Input Inter Pair Skew Margin
-
-
15
UI
LVDS Differential Output Transition Time
-
0.6
1.5
ns
LVDS Output Data Position0
-0.25
0
0.25
ns
LVDS Output Data Position1
LVDS Output Data Position2
LVDS Output Data Position3
LVDS Output Data Position4
LVDS Output Data Position5
LVDS Output Data Position6
tTCIP/7-0.25
tTCIP/7
tTCIP/7+0.25 ns
2×tTCIP/7-0.25 2×tTCIP/7 2×tTCIP/7+0.25 ns
3×tTCIP/7-0.25 3×tTCIP/7 3×tTCIP/7+0.25 ns
4×tTCIP/7-0.25 4×tTCIP/7 4×tTCIP/7+0.25 ns
5×tTCIP/7-0.25 5×tTCIP/7 5×tTCIP/7+0.25 ns
6×tTCIP/7-0.25 6×tTCIP/7 6×tTCIP/7+0.25 ns
Lane0/1 LVDS Output Clock Skew
Input Data to Output Clock Delay
-
-
50
ps
(178+68×n)
(178+68×n)
×tRBIT-5 (1)
-
×tRBIT+5 (1)
ns
Power On to PDN High Delay
0
-
-
ns
PDN High to HTPDN Low Delay
-
-
1
us
PDN Low to HTPDN High Delay
Training Pattern Input to LOCKN Low
-
-
1
us
Delay
-
-
10
ms
PDN Low to LOCKN High Delay
-
-
10
us
LOCKN Low to LVDS Output Delay
-
-
1
ms
LOCKN High to LVDS High-Z Delay
-
-
0
ns
(1) n =3, 4, and 5 for 6/8bit, 10bit, and 12bit mode, respectively.
Table 17. THCV216 Switching Characteristics
THCV215-216_Rev.2.70_E
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