THCV231_16 Datasheet, PDF (48/56 Pages) THine Electronics, Inc. – The THCV231 and THCV236 are designed to support video data transmission between the host and display.

Lock and Unlock Sequence
VDD
CLKIN
D11-D0
HSYNC,VSYNC
HTPDN
Register(0x00 bit0)
on THCV236
PDN
LOCKN
Register(0x00 bit1)
on THCV236
TXP/N
Data
Data
tTPD tTPLL0
tTNP1
tTNP0
tTPLL1
Fix to CAPINA
Training
pattern
Normal
pattern
Figure 23. THCV231 Lock/Unlock Sequence
Training
pattern
VDD
PDN0
tRPD
HTPDN
Register(0x00 bit0)
tRHPD0
tRHPD1
RXP/N
Training
pattern
Normal
pattern
LOCKN
Register(0x00 bit1)
CLKOUT
(OUTSEL=0)
Low
CLKOUT
(OUTSEL=1)
Low
D11-D0
HSYNC,VSYNC
tRPLL0
tRLCK0
Invalid
Clock
Permanent Clock
(Internal OSC Clock)
tROSC0
Low
tOSC/N
(N=1,2,4,8)(*1)
Low
tROSC1
Pixel Clock
Valid
Clock
Pixel Clock
Valid
Clock
tRPLL1 tRLCK1
Data
Low
Permanent Clock
(Internal OSC Clock)
Low
tROSC2
InValid Data
*1 N depends on setting of OUTSEL_SETTING register (0x6D bit1,0). See Register Map (Table 36)
Figure 24. THCV236 Lock/Unlock Sequence
THCV231_THCV236_Rev.2.30_E
Copyright©2016 THine Electronics, Inc.
48/56
THine Electronics, Inc.
Security E