THCV231_16 Datasheet, PDF(30/56 Page) THine Electronics, Inc. – The THCV231 and THCV236 are designed to support video data transmission between the host and display.

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THCV231_16 Datasheet, PDF (30/56 Pages) THine Electronics, Inc. – The THCV231 and THCV236 are designed to support video data transmission between the host and display.

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Address

(Hex)

0x00

0x01

0x02

0x03

Table 31. Sub-Link Master Control Register

Bit#

R/W

Default

(Hex)

Description

7:3 R

0x00

Reserved

INT

LOCKN

7:1 R

0 RW

0x00

HTPDN

SFTRST

7 RW

2WIRE_ACS_END_INT

6 RW

LOCKN_INT

5 RW

HTPDN_INT

SLAVESIDE_INT

GPIO_INT

2 RW

COMERR_INT

1 RW

2WIRE_TIMEOUT_INT

0 RW

SLINK_TIMEOUT_INT

(*2)

2WIRE_ACS_END_INT_ENABLE

6 RW

LOCKN_INT_ENABLE

5 RW

HTPDN_INT_ENABLE

4 RW

SLAVESIDE_INT_ENABLE

3 RW

GPIO_INT_ENABLE

2 RW

COMERR_INT_ENABLE

1 RW

2WIRE_TIMEOUT_INT_ENABLE

0 RW

SLINK_TIMEOUT_INT_ENABLE

Interrupt condition

0: Steady state

1: Interrupt occurred(INT output =L)

V-by-OneÂ® HS lock status

0: Locked (LOCKN=L)

1: Unlocked

V-by-OneÂ® HS plug status

0: Connected (HTPDN=L)

1: Not connected or Rx inactive

Reserved

Sub-Link soft reset

Write 1: Sub-Link reset

Automatically cleared into 0 after reset action. 0 is always read.

Cause of interrupt access completion to register of Sub-Link Slave or

Remote side 2-wire serial Slave device

0: Access incomplete

1: Access complete

Any write action: clear this bit into 0

Cause of interrupt LOCKN

0: No change on lock status ever

1: Lock status has once changed

Any write action: clear this bit into 0

Cause of interrupt HTPDN

0: No change on plug status ever

1: Plug status has once changed

Any write action: clear this bit into 0

Cause of interrupt Sub-Link Slave side

0: No interrupt at Sub-Link Slave ever

1: Interrupted at Sub-Link Slave once

This bit is cleared when cause of interrupt register at Sub-Link Slave (0x82)

is cleared.

Cause of interrupt Sub-Link Master GPIO

0: No change in Master GPIO inputs ever

1: Master GPIO inputs have once changed.

This bit is cleared when GPIOn_INPUT_MONITOR (n=4~0) register (0x41)

is read.

Cause of interrupt Sub-Link communication Error

0: No communication error on Sub-Link ever

1: Communication error on Sub-Link once happened

Any write action: clear this bit into 0

Cause of interrupt 2-wire serial time out

0: 2-wire serial access in time ever

1: 2-wire serial access has once had time out

Any write action: clear this bit into 0

Cause of interrupt Sub-Link time out

0: Sub-Link access in time ever

1: Sub-Link has once had time out

Any write action: clear this bit into 0

0: "2WIRE_ACS_END_INT" is blocked to take interrupt action

1: "2WIRE_ACS_END_INT" is allowed to take action on INT output

0: "LOCKN_INT" is blocked to take interrupt action

1: "LOCKN_INT" is allowed to take action on INT output

0: "HTPDN_INT" is blocked to take interrupt action

1: "HTPDN_INT" is allowed to take action on INT output

0: "SLAVESIDE_INT" is blocked to take interrupt action

1: "SLAVESIDE_INT" is allowed to take action on INT output

0: "GPIO_INT" is blocked to take interrupt action

1: "GPIO_INT" is allowed to take action on INT output

0: "COMERR_INT" is blocked to take interrupt action

1: "COMERR_INT" is allowed to take action on INT output

0: "2WIRE_TIMEOUT_INT" is blocked to take interrupt action

1: "2WIRE_TIMEOUT_INT" is allowed to take action on INT output

0: "SLINK_TIMEOUT_INT" is blocked to take interrupt action

1: "SLINK_TIMEOUT_INT" is allowed to take action on INT output

These registers are always active independent of Interrupt permission register.

When No clock stretching mode, the value is 1 fixed, otherwise 0 fixed

Note

(*1)

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