THCV231_16 Datasheet, PDF (37/56 Pages) THine Electronics, Inc. – The THCV231 and THCV236 are designed to support video data transmission between the host and display.

Table 36. THCV236 Main-Link Control Register Map
Address (Hex)
Sub-Link
Master
Bit#
R/W
Default
(Hex)
Name
Description
Note
0x50
MAINMODE setting
7
RW
(*1)
MAINMODE
0: V-by-One^® HS Mode
-
1: Sync Free Mode
HFSEL setting
6
RW
(*1)
HFSEL
0: High Frequency Mode Disable
-
1: High Frequency Mode Enable
COL1 setting
when MAINMODE =0
5
RW
0
COL1
0: Color Space Converter Disable
1: Color Space Converter Enable
-
when MAINMODE =1
Data Width Setting. See Table 15.
4
RW
(*1)
COL0
COL0 setting
Data Width Setting. See Table 15.
-
3
RW
0
Reserved
-
2:1
RW
0x0
Reserved
-
TTLDRV setting
0
RW
0
TTLDRV
0: Weak Drive Strength
-
1: Normal Drive Strength
0x51
7:6
R
0x0
Reserved
-
SSEN setting
5
RW
0
SSEN
0: SSCG Disable
1: SSCG Enable
(*2)
4:0
RW
0x05 SPREAD
SSCG modulation depth setting
Spread depth = ±SPREAD x 0.1% (Center Spread)
0x52
7:4
R
0x0
Reserved
-
3:0
RW
0xD
FMOD
SSCG Modulation Frequency Setting
-
0x53
7:2
R
0x00
Reserved
-
1
RW
0
Reserved
-
Main-Link / Sub-Link Field BET Mode select
0
RW
0
BET_SEL
0: Main-Link Field BET Mode
-
1: Sub-Link Field BET Mode
0x54
7
R
0
Reserved
-
6:0
RW
0x3E
Reserved. Must be default setting.
-
0x55
-0x6C
7:0
RW
0x0
Reserved
-
0x6D
7:3
R
0x00
Reserved
-
Permanent Clock Output Enable setting
2
RW
0
OUTSEL_ENABLE 0: Permanent Clock Output Disable
-
1: Permanent Clock Output Enable
Permanent Clock Frequency setting
00: 80MHz (Clock Period : tOSC)
1:0
RW
0x1
OUTSEL_SETTING 01: 40MHz (Clock Period : tOSC/2)
(*3)
10: 20MHz (Clock Period : tOSC/4)
11: 10MHz (Clock Period : tOSC/8)
0x6E
7:1
R
0x00
Reserved
-
0
RW
1
Reserved. Must be 1
-
0x6F
7:0
R
0x00
Reserved
-
0x70
7:2
R
0x00
Reserved
-
1
RW
0
Reserved. Must be 0
-
SSCG PLL setting register Enable
0
RW
0
PLL_SET_EN
1: Enable
-
0: Disable
0x71
-0x75
7:0
R
0x00
Reserved
-
0x76
7:6
R
0x0
Reserved
-
5:0
RW
0x00 PLL_SET0
SSCG PLL setting
(*4)
0x77
7:4
R
0x0
Reserved
-
3:0
RW
0x0
Reserved. Must be default setting.
-
0x78
7:0
RW
0xXX PLL_SET1
SSCG PLL setting
(*4)
0x79
-0x7B
7:0
R
0x00
Reserved. Must be default setting.
-
0x7C
7:6
R
0x0
Reserved
-
5:0
RW
0xXX PLL_SET2
SSCG PLL setting
(*4)
0x7D
-0x7F
7:0
R
0xXX
Reserved. Must be default setting.
-
*1
Default value depends on RXDEFSEL setting when Power on sequence. RXDEFSEL=1 → default value is 0 , RXDEFSEL=0 → default value is 1.
*2
SSEN=1 and SPREAD=0 setting is forbidden
*3
Described value is typical value. It has variation in the range from min spec value to max spec value of tOSC.
*4
See Table 8, Table 16
THCV231_THCV236_Rev.2.30_E
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