71M6533 Datasheet, PDF (87/124 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS_6533_6534_004
PREG[16:0]
201C[2:0]
201D[7:0]
201E[7:2]
PRE_SAMPS[1:0] 2001[7:6]
QREG[1:0]
RST_SUBSEC
RTCA_ADJ[6:0]
RTC_SEC[5:0
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
201E[1:0]
2010[0]
2011[6:0]
2015
2016
2017
2018
2019
201A
201B
RTM_E
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
SECURE
2002[3]
2060[9:8]
2061[7:0]
2062[9:8]
2063[7:0]
2064[9:8]
2064[7:0]
2065[9:8]
2066[7:0]
SFRB2[6]
71M6533/71M6534 Data Sheet
4
4 R/W RTC adjust. See Section 1.4.3 Real-Time Clock (RTC) for additional details.
0
0 R/W
0x0FFBF ≤ PREG ≤ 0x10040
0
0 R/W _{PREG[16:0] and QREG[1:0] are separate in hardware but can be programmed with a}
single number calculated by the MPU.
0
0 R/W The duration of the pre-summer, in samples.
PRE_SAMPS[1:0]
00
01
10
11
Pre-Summer Duration
42
50
84
100
0
0 R/W RTC adjust. See Section 1.4.3 Real-Time Clock (RTC) for additional details.
0
0 R/W The sub-second counter is restarted when a 1 is written to this bit.
40
– R/W Analog RTC adjust. See Section 1.4.3 Real-Time Clock (RTC) for additional details.
*
NV _{R/W These are the year, month, day, hour, minute and second parameters of the RTC.}
*
NV
Writing to these registers sets the time. Each write to one of these registers must be
*
NV
preceded by a write to 0x201F (WE). Valid values for each parameter are:
*
NV
SEC: 00 to 59, MIN: 00 to 59, HR: 00 to 23 (00 = Midnight)
*
NV
DAY: 01 to 07 (01 = Sunday), DATE: 01 to 31, MO: 01 to 12
*
NV
YR: 00 to 99 (00 and all others divisible by 4 are leap years)
*
NV
Values in the RTC registers are undefined when the IC powers up without a battery but
are maintained through mission and battery modes when a sufficient voltage is main-
tained at the VBAT pin. Write operations to these registers are delayed by one
second.
* no change of value at reset if voltage at VBAT is within specification.
0
0 R/W Real Time Monitor enable (RTM). When 0, the RTM output is low.
0
0 R/W The four RTM probes. Before each CE code pass, the values of these registers are
0
0
serially output on the RTM pin. The RTM registers are ignored when RTM_E = 0.
0
0
0
0
0
0
0
0
0
0
0
0
0
– R/W When set, enables security provisions that prevent external reading of flash memory
and CE program RAM (zeros will be returned if the memory is read). It should be set
while PREBOOT is set. This bit is cleared when the flash is mass-erased and on chip
reset. The bit may only be set, attempts to write zero are ignored.
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
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