71M6533 Datasheet, PDF (83/124 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS_6533_6534_004
LCD_BITMAP
[50:48]
LCD_BITMAP
[63:61],
[59:56]*
2026[2:0]
0
2027[7:5,3:0] 0
LCD_BITMAP 2028[7:0]
0
[71:64]
LCD_BLKMAP18 205A[3:0]
0
[3:0]
LCD_CLK[1:0] 2021[1:0]
0
LCD_DAC[2:0] 20AB[3:1]
0
LCD_E
2021[5]
0
71M6533/71M6534 Data Sheet
L R/W _{Configuration for DIO30/SEG50 through DIO28/SEG48. LCD_BITMAP[48] correspond-}
ing to DIO28/SEG48 is only applicable to the 71M6534. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin.
L R/W _{Configuration for DIO43/SEG63 through DIO41/SEG61 and DIO39/SEG59 through}
DIO36/SEG56. LCD_BITMAP[62] corresponding to DIO42/SEG62 and
LCD_BITMAP[59:56] corresponding to DIO39/SEG59 through DIO36/SEG56 are only
applicable to the 71M6534. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin.
L R/W _{Configuration for DIO51/SEG71 through DIO44/SEG64. LCD_BITMAP[66] correspond-}
ing to DIO46/SEG66 is only applicable to the 71M6534. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin.
L R/W _{Identifies which segments connected to SEG18 should blink. 1 means blink. The}
most significant bit corresponds to COM3, the least significant bit to COM0.
L R/W _{Sets the LCD clock frequency for the COM/SEG pins (not the frame rate) according to}
the following (f_w = 32768 Hz):
00 = f_w/512, 01 = f_w/256, 10 = f_w/128, 11 = f_w/64
L R/W _{LCD contrast control DAC. Adjusts the LCD voltage in steps of 0.2 V from V3P3SYS}
(mission mode) or VBAT (brownout/LCD modes).
LCD_DAC[2:0] Resulting LCD Voltage
000
V3P3 or VBAT
001
V3P3 or VBAT – 0.2V
010
V3P3 or VBAT – 0.4V
011
V3P3 or VBAT – 0.6V
100
V3P3 or VBAT – 0.8V
101
V3P3 or VBAT – 1.0V
110
V3P3 or VBAT – 1.2V
111
V3P3 or VBAT – 1.4V
L R/W _{Enables the LCD display. When disabled, VLC2, VLC1 and VLC0 are ground as are}
the COM and SEG outputs.
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
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